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PDF AD9235 Data sheet ( Hoja de datos )
| Número de pieza | AD9235 | |
| Descripción | 3V A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD9235 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Data Sheet
FEATURES
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 70 dBc to Nyquist at 65 MSPS
SFDR = 85 dBc to Nyquist at 65 MSPS
Low power: 300 mW at 65 MSPS
Differential input with 500 MHz bandwidth
On-chip reference and SHA
DNL = ±0.4 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
APPLICATIONS
Ultrasound equipment
IF sampling in communications receivers
IS-95, CDMA-One, IMT-2000
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
GENERAL DESCRIPTION
The AD9235 is a family of monolithic, single 3 V supply, 12-bit,
20/40/65 MSPS analog-to-digital converters (ADCs). This
family features a high performance sample-and-hold amplifier
(SHA) and voltage reference. The AD9235 uses a multistage
differential pipelined architecture with output error correction
logic to provide 12-bit accuracy at 20/40/65 MSPS data rates
and guarantee no missing codes over the full operating
temperature range.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and offsets including single-ended
applications. It is suitable for multiplexed systems that switch
full-scale voltage levels in successive channels and for sampling
single-channel inputs at frequencies well beyond the Nyquist rate.
Combined with power and cost savings over previously available
ADCs, the AD9235 is suitable for applications in communica-
tions, imaging, and medical ultrasound.
A single-ended clock input is used to control all internal
conversion cycles. A duty cycle stabilizer (DCS) compensates
for wide variations in the clock duty cycle while maintaining
excellent overall ADC performance. The digital output data is
presented in straight binary or twos complement formats. An
out-of-range (OTR) signal indicates an overflow condition that
12-Bit, 20/40/65 MSPS
3 V A/D Converter
AD9235
FUNCTIONAL BLOCK DIAGRAM
AVDD
DRVDD
VIN+
VIN–
REFT
REFB
SHA
VREF
SENSE
REF
SELECT
MDAC1
4
A/D
8-STAGE
1 1/2-BIT
PIPELINE
16
A/D
3
CORRECTION LOGIC
12
OUTPUT BUFFERS
AD9235
CLOCK
DUTY CYCLE
STABILIZER
0.5V
MODE
SELECT
OTR
D11
D0
AGND
CLK
PDWN MODE DGND
Figure 1.
can be used with the most significant bit to determine low or
high overflow.
Fabricated on an advanced CMOS process, the AD9235 is avail-
able in a 28-lead TSSOP and a 32-lead LFCSP and is specified
over the industrial temperature range (–40°C to +85°C).
PRODUCT HIGHLIGHTS
1. The AD9235 operates from a single 3 V power supply and
features a separate digital output driver supply to accommo-
date 2.5 V and 3.3 V logic families.
2. Operating at 65 MSPS, the AD9235 consumes a low 300 mW.
3. The patented SHA input maintains excellent performance for
input frequencies up to 100 MHz and can be configured for
single-ended or differential operation.
4. The AD9235 pinout is similar to the AD9214-65, a 10-bit,
65 MSPS ADC. This allows a simplified upgrade path from
10 bits to 12 bits for 65 MSPS systems.
5. The clock DCS maintains overall ADC performance over a
wide range of clock pulse widths.
6. The OTR output bit indicates when the signal is beyond the
selected input range.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no re-
sponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
1 page  
AD9235
Data Sheet
DIGITAL SPECIFICATIONS
Table 2.
Parameter
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
LOGIC OUTPUTS1
DRVDD = 3.3 V
High-Level Output Voltage
(IOH = 50 µA)
High-Level Output Voltage
(IOH = 0.5 mA)
Low-Level Output Voltage
(IOL = 1.6 mA)
Low-Level Output Voltage
(IOL = 50 µA)
DRVDD = 2.5 V
High-Level Output Voltage
(IOH = 50 µA)
High-Level Output Voltage
(IOH = 0.5 mA)
Low-Level Output Voltage
(IOL = 1.6 mA)
Low-Level Output Voltage
(IOL = 50 µA)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test
Level
IV
IV
IV
IV
V
IV
IV
IV
IV
IV
IV
IV
IV
AD9235BRU/BCP-20
Min Typ Max
2.0
–10
–10
2
0.8
+10
+10
3.29
3.25
0.2
0.05
2.49
2.45
0.2
0.05
AD9235BRU/BCP-40
Min Typ Max
2.0
–10
–10
2
0.8
+10
+10
3.29
3.25
0.2
0.05
2.49
2.45
0.2
0.05
AD9235BRU/BCP-65
Min Typ Max
2.0
–10
–10
2
0.8
+10
+10
3.29
3.25
0.2
0.05
2.49
2.45
0.2
0.05
Unit
V
V
µA
µA
pF
V
V
V
V
V
V
V
V
1 Output voltage levels measured with 5 pF load on each output.
SWITCHING SPECIFICATIONS
Table 3.
Parameter
Test AD9235BRU/BCP-20
Temp Level Min Typ Max
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Full VI
20
Minimum Conversion Rate
Full V
1
CLK Period
Full V
50.0
CLK Pulse-Width High1
Full V
15.0
CLK Pulse-Width Low1
Full V
15.0
DATA OUTPUT PARAMETERS
Output Delay2 (tPD)
Full V
3.5
Pipeline Delay (Latency)
Full V
7
Aperture Delay (tA)
Full V
1.0
Aperture Uncertainty Jitter (tJ) Full V
0.5
Wake-Up Time3
Full V
3.0
OUT-OF-RANGE RECOVERY TIME Full V
1
AD9235BRU/BCP-40
Min Typ Max
40
1
25.0
8.8
8.8
3.5
7
1.0
0.5
3.0
1
AD9235BRU/BCP-65
Min Typ Max
65
1
15.4
6.2
6.2
3.5
7
1.0
0.5
3.0
2
Unit
MSPS
MSPS
ns
ns
ns
ns
Cycles
ns
ps rms
ms
Cycles
1 For the AD9235-65 model only, with duty cycle stabilizer enabled. DCS function not applicable for -20 and -40 models.
2 Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output.
3 Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.
Rev. D | Page 4 of 40
5 Page 
AD9235
EQUIVALENT CIRCUITS
AVDD
VIN+, VIN–
Figure 5. Equivalent Analog Input Circuit
AVDD
MODE
20kΩ
Figure 6. Equivalent MODE Input Circuit
Data Sheet
DRVDD
D11–D0,
OTR
Figure 7. Equivalent Digital Output Circuit
AVDD
CLK,
PDWN
Figure 8. Equivalent Digital Input Circuit
Rev. D | Page 10 of 40
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9235.PDF ] | |
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