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PDF KH25L3206E Data sheet ( Hoja de datos )
| Número de pieza | KH25L3206E | |
| Descripción | 32M-BIT [x 1 / x 2] CMOS SERIAL FLASH | |
| Fabricantes | macronix | |
| Logotipo |  |
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KH25L3206E
KH25L3206E DATASHEET
P/N: PM1867
REV. 1.2, NOV. 28, 2013
1
1 page  
KH25L3206E
FEATURES
32M-BIT [x 1 / x 2] CMOS SERIAL FLASH
GENERAL
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 33,554,432 x 1 bit structure or 16,777,216 x 2 bits (Dual Output mode) structure
• 1024 Equal Sectors with 4K byte each
- Any Sector can be erased individually
• 64 Equal Blocks with 64K byte each
- Any Block can be erased individually
• Program Capability
- Byte base
- Page base (256 bytes)
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
- Fast access time: 86MHz serial clock
- Serial clock of Dual Output mode : 80MHz
- Fast program time: 0.6ms(typ.) and 3ms(max.)/page
- Byte program time: 9us (typical)
- Fast erase time: 40ms(typ.) /sector ; 0.4s(typ.) /block
• Low Power Consumption
- Low active read current: 25mA(max.) at 86MHz
- Low active programming current: 15mA (typ.)
- Low active sector erase current: 9mA (typ.)
- Standby current: 15uA (typ.)
- Deep power-down mode 2uA (typical)
• Typical 100,000 erase/program cycles
• 20 years of data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP3~BP0 status bit defines the size of the area to be software protection against program and erase instruc-
tions
- Additional 512 bits secured OTP for unique identifier
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
P/N: PM1867
REV. 1.2, NOV. 28, 2013
5
5 Page 
KH25L3206E
DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or pro-
gramming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specific command se-
quences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC power-
up and power-down or from system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before is-
suing other command to change data. The WEL bit will return to reset stage under following situations:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Sector Erase (SE) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from deep power down mode command (RDP) and Read Electronic Sig-
nature command (RES).
• Advanced Security Features: there are some protection and security features which protect content from inad-
vertent write and hostile access.
I. Block lock protection
- The Software Protected Mode (SPM):
KH25L3206E: use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The proect-
ed area definition is shown as "Table 2. Protected Area Sizes", the protected areas are more flexible which may
protect various area by setting value of BP0-BP3 bits.
Please refer to "Table 2. Protected Area Sizes".
- The Hardware Proteced Mode (HPM) uses WP# to protect the KH25L3206E: BP3-BP0 bits and SRWD bit.
P/N: PM1867
REV. 1.2, NOV. 28, 2013
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet KH25L3206E.PDF ] | |
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