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PDF RM7000 Data sheet ( Hoja de datos )
| Número de pieza | RM7000 | |
| Descripción | Microprocessor | |
| Fabricantes | PMC-Sierra | |
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RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet
Released
RM7000
RM7000™ Microprocessor with On-Chip
Secondary Cache
Datasheet
Proprietary and Confidential
Issue 1, January 2001
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002175, Issue 1
1 page  
RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet
Released
Table of Contents
Legal Information ...........................................................................................................................2
Revision History .............................................................................................................................3
Document Conventions .................................................................................................................4
Table of Contents ..........................................................................................................................5
List of Figures ................................................................................................................................7
List of Tables .................................................................................................................................8
1 Features ..................................................................................................................................9
2 Block Diagram .......................................................................................................................10
3 Description ............................................................................................................................11
4 Hardware Overview ...............................................................................................................12
4.1 CPU Registers .............................................................................................................12
4.2 Superscalar Dispatch ...................................................................................................12
4.3 Pipeline ........................................................................................................................13
4.4 Integer Unit ..................................................................................................................14
4.5 ALU ..............................................................................................................................15
4.6 Integer Multiply/Divide ..................................................................................................15
4.7 Floating-Point Coprocessor ..........................................................................................16
4.8 Floating-Point Unit .......................................................................................................16
4.9 Floating-Point General Register File ............................................................................16
4.10 System Control Coprocessor (CP0) .............................................................................17
4.11 System Control Coprocessor Registers .......................................................................18
4.12 Virtual to Physical Address Mapping ............................................................................19
4.13 Joint TLB ......................................................................................................................20
4.14 Instruction TLB .............................................................................................................20
4.15 Data TLB ......................................................................................................................20
4.16 Cache Memory .............................................................................................................21
4.17 Instruction Cache .........................................................................................................21
4.18 Data Cache ..................................................................................................................21
4.19 Secondary Cache ........................................................................................................23
4.20 Secondary Caching Protocols ......................................................................................24
4.21 Tertiary Cache .............................................................................................................24
4.22 Cache Locking .............................................................................................................26
4.23 Cache Management .....................................................................................................26
4.24 Primary Write Buffer .....................................................................................................27
4.25 System Interface ..........................................................................................................27
4.26 System Address/Data Bus ...........................................................................................28
4.27 System Command Bus ................................................................................................28
4.28 Handshake Signals ......................................................................................................28
4.29 System Interface Operation .........................................................................................29
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002175, Issue 1
5
5 Page 
RM7000™ Microprocessor with On-Chip Secondary Cache Datasheet
Released
3 Description
PMC-Sierra’s RM7000 is a highly integrated symmetric superscalar microprocessor capable of
issuing two instructions each processor cycle. It has two high-performance 64-bit integer units as
well as a high-throughput, fully pipelined 64-bit floating point unit. To keep its multiple execution
units running efficiently, the RM7000 integrates not only 16 KB 4-way set associative instruction
and data caches but backs them up with an integrated 256 KB 4-way set associative secondary as
well. For maximum efficiency, the data and secondary caches are write-back and non-blocking. An
optional external tertiary cache provides high-performance capability even in applications having
very large data sets.
A RM5200 Family compatible, operating system friendlymemory management unit with a 64/48-
entry fully associative TLB and a high-performance 64-bit system interface supporting multiple
outstanding reads with out-of-order return and hardware prioritized and vectored interrupts round
out the main features of the processor.
The RM7000 is ideally suited for high-end embedded control applications such as
internetworking, high-performance image manipulation, high-speed printing, and 3-D
visualization. The RM7000 is also applicable to the low end workstation market where its
balanced integer and floating-point performance and direct support for a large tertiary cache (up to
8 MB) provide outstanding price/performance.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002175, Issue 1
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet RM7000.PDF ] | |
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