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Número de pieza | RM7000A | |
Descripción | Microprocessor | |
Fabricantes | PMC-Sierra | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de RM7000A (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
No Preview Available ! RM7000A™ Microprocessor with On-Chip Secondary Cache Data Sheet
Released
RM7000A
RM7000A™ Microprocessor with On-
Chip Secondary Cache
Data Sheet
Proprietary and Confidential
Released
Issue 2, May 2001
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002227, Issue 2
1 page RM7000A™ Microprocessor with On-Chip Secondary Cache Data Sheet
Released
Table of Contents
Legal Information ...........................................................................................................................2
Revision History .............................................................................................................................3
Document Conventions .................................................................................................................4
Table of Contents .......................................................................................................................... 5
List of Figures ................................................................................................................................7
List of Tables .................................................................................................................................8
1 Features ..................................................................................................................................9
2 Block Diagram .......................................................................................................................10
3 Description ............................................................................................................................11
4 Hardware Overview ...............................................................................................................12
4.1 CPU Registers .............................................................................................................12
4.2 Superscalar Dispatch ...................................................................................................12
4.3 Pipeline ........................................................................................................................13
4.4 Integer Unit ..................................................................................................................14
4.5 ALU ..............................................................................................................................15
4.6 Integer Multiply/Divide ..................................................................................................15
4.7 Floating-Point Coprocessor ..........................................................................................16
4.8 Floating-Point Unit .......................................................................................................16
4.9 Floating-Point General Register File ............................................................................17
4.10 System Control Coprocessor (CP0) .............................................................................18
4.11 System Control Coprocessor Registers .......................................................................18
4.12 Virtual to Physical Address Mapping ............................................................................19
4.13 Joint TLB ......................................................................................................................20
4.14 Instruction TLB .............................................................................................................21
4.15 Data TLB ......................................................................................................................21
4.16 Cache Memory .............................................................................................................21
4.17 Instruction Cache .........................................................................................................22
4.18 Data Cache ..................................................................................................................22
4.19 Secondary Cache ........................................................................................................24
4.20 Secondary Caching Protocols ......................................................................................24
4.21 Tertiary Cache .............................................................................................................25
4.22 Cache Locking .............................................................................................................26
4.23 Cache Management .....................................................................................................27
4.24 Primary Write Buffer .....................................................................................................27
4.25 System Interface ..........................................................................................................27
4.26 System Address/Data Bus ...........................................................................................28
4.27 System Command Bus ................................................................................................28
4.28 Handshake Signals ......................................................................................................29
4.29 System Interface Operation .........................................................................................29
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers' Internal Use
Document ID: PMC-2002227, Issue 2
5
5 Page RM7000A™ Microprocessor with On-Chip Secondary Cache Data Sheet
Released
3 Description
PMC-Sierra’s RM7000A is a highly integrated symmetric superscalar microprocessor capable of
issuing two instructions each processor cycle. It has two high-performance 64-bit integer units as
well as a high-throughput, fully pipelined 64-bit floating point unit.
The RM7000A integrates 16 KB 4-way set associative instruction and data caches along with an
integrated 256 KB 4-way set associative secondary. The primary data and secondary caches are
write-back and non-blocking. An optional external tertiary cache provides high-performance
capability even in applications with very large data sets.
The memory management unit contains a 64/48-entry fully associative TLB and a 64-bit system
interface supporting multiple outstanding reads with out-of-order return and hardware prioritized
and vectored interrupts.
The RM7000A ideally suits high-end embedded control applications such as internetworking,
high-performance image manipulation, high-speed printing, and 3-D visualization. The RM7000A
is also applicable to the low end workstation market where its balanced integer and floating-point
performance and direct support for a large tertiary cache (up to 8 MB) provide outstanding price/
performance.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002227, Issue 2
11
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet RM7000A.PDF ] |
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