|
|
PDF RM7065A Data sheet ( Hoja de datos )
| Número de pieza | RM7065A | |
| Descripción | Microprocessor | |
| Fabricantes | PMC-Sierra | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de RM7065A (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
RM7065A
RM7065A™ Microprocessor with On-
Chip Secondary Cache
Data Sheet
Preliminary
Issue 2, June 2001
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2010145, Issue 2
1 page  
RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Table of Contents
1 Features ..................................................................................................................................9
2 Block Diagram .......................................................................................................................10
3 Description ............................................................................................................................11
4 Hardware Overview ...............................................................................................................12
4.1 CPU Registers .............................................................................................................12
4.2 Superscalar Dispatch ...................................................................................................12
4.3 Pipeline ........................................................................................................................13
4.4 Integer Unit ..................................................................................................................14
4.5 ALU ..............................................................................................................................15
4.6 Integer Multiply/Divide ..................................................................................................15
4.7 Floating-Point Coprocessor ..........................................................................................16
4.8 Floating-Point Unit .......................................................................................................16
4.9 Floating-Point General Register File ............................................................................17
4.10 System Control Coprocessor (CP0) .............................................................................18
4.11 System Control Coprocessor Registers .......................................................................18
4.12 Virtual to Physical Address Mapping ............................................................................19
4.13 Joint TLB ......................................................................................................................20
4.14 Instruction TLB .............................................................................................................21
4.15 Data TLB ......................................................................................................................21
4.16 Cache Memory .............................................................................................................22
4.17 Instruction Cache .........................................................................................................22
4.18 Data Cache ..................................................................................................................22
4.19 Secondary Cache ........................................................................................................24
4.20 Secondary Caching Protocols ......................................................................................24
4.21 Cache Locking .............................................................................................................25
4.22 Cache Management .....................................................................................................26
4.23 Primary Write Buffer .....................................................................................................26
4.24 System Interface ..........................................................................................................26
4.25 System Address/Data Bus ...........................................................................................27
4.26 System Command Bus ................................................................................................27
4.27 Handshake Signals ......................................................................................................28
4.28 System Interface Operation .........................................................................................28
4.29 Data Prefetch ...............................................................................................................30
4.30 Enhanced Write Modes ................................................................................................31
4.31 External Requests ........................................................................................................31
4.32 Test/Breakpoint Registers ............................................................................................31
4.33 Performance Counters .................................................................................................32
4.34 Interrupt Handling ........................................................................................................34
4.35 Standby Mode ..............................................................................................................36
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2010145, Issue 2
5
5 Page 
RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
3 Description
PMC-Sierra’s RM7065A is a highly integrated symmetric superscalar microprocessor capable of
issuing two instructions each processor cycle. It has two high-performance 64-bit integer units as
well as a high-throughput, fully pipelined 64-bit floating point unit.
The RM7065A integrates 16 KB 4-way set associative instruction and data caches along with an
integrated 256 KB 4-way set associative secondary. The primary data and secondary caches are
write-back and non-blocking.
The memory management unit contains a 64/48-entry fully associative TLB and a 64-bit system
interface supporting multiple outstanding reads with out-of-order return and hardware prioritized
and vectored interrupts.
The RM7065A ideally suits high-end embedded control applications such as internetworking,
high-performance image manipulation, high-speed printing, and 3-D visualization. The RM7065A
is also applicable to the low end workstation market where its balanced integer and floating-point
performance provide outstanding price/performance.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2010145, Issue 2
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet RM7065A.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| RM7065A | Microprocessor | PMC-Sierra |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |