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PDF HI-6138 Data sheet ( Hoja de datos )
| Número de pieza | HI-6138 | |
| Descripción | Compact Multi-Terminal Device | |
| Fabricantes | HOLTIC | |
| Logotipo |  |
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November, 2016
MAMBATM: HI-6138
3.3V BC / MT / RT MIL-STD-1553 / MIL-STD-1760
Compact Multi-Terminal Device with SPI Host Interface
GENERAL DESCRIPTION
The 3.3V CMOS HI-6138 device is a member of Holt’s
MIL-STD-1553 MAMBATM family and provides a complete
single- or multi-function interface between a host
processor and MIL-STD-1553B bus. Each IC contains
a Bus Controller (BC), a Bus Monitor Terminal (MT)
and a Remote Terminal (RT). Any combination of the
contained 1553 functions can be enabed for concurrent
operation. The enabled terminals communicate with the
MIL-STD-1553 buses through a shared on-chip dual
bus transceiver and external transformers. The user
allocates 16K bytes of on-chip static RAM between
devices to suit application requirements.
The HI-6138 communicates with the host via a 40 MHz
4-wire serial peripheral interface (SPI). Programmable
interrupts provide terminal status to the host processor.
Circular data buffers in RAM have interrupts for rollover
and programmable “level attained”.
• 64-Word Interrupt Log Buffer queues the most
recent 32 interrupts. Hardware-assisted interrupt
decoding quickly identifies interrupt sources.
• Built-in self-test for protocol logic, digital signal
paths and internal RAM.
• Optional self-initialization at reset uses external
serial EEPROM.
• ±8kV ESD Protection (HBM, all pins).
• Two temperature ranges: -40oC to +85oC, or
-55oC to +125oC with optional burn-in.
• RoHS compliant and Tin / Lead options available.
PIN CONFIGURATION (TOP)
The HI-6138 can be configured for automatic self-
initialization after reset. A dedicated SPI port reads
data from an external serial EEPROM to fully configure
registers and RAM and optionally start execution for any
subset of one to three terminal devices.
FEATURES
• Concurrent multi-terminal operation for one to
three MIL-STD-1553B functions: BC, MT and/or
RT.
• 8K x 17-bit words internal static RAM with parity
• Autonomous terminal operation requires minimal
host intervention.
• 40 MHz SPI Host Interface.
• MIL-STD-1760 option sets Busy bit in Status
Word response during initialization.
• World’s smallest MIL-STD-1553 terminal, QFN
package measures just 6mm x 6mm.
• Fully programmable Bus Controller with 28 op
code instruction set.
• Simple Monitor Terminal (SMT) Mode records
commands and data separately, with 16-bit or 48-
bit time tagging.
• Independent 16-bit time tag counters and clock
sources for all modes. The Bus Controller and
Monitor also have 32- and 48-bit time count
options, respectively.
MODE - 1
IRQ - 2
ACKIRQ - 3
MODE1760 - 4
READY - 5
VCC - 6
GND - 7
ACTIVE - 8
RTSSF - 9
AUTOEN - 10
TXINHA - 11
TXINHB - 12
HI-6138PCIF
HI-6138PCTF
HI-6138PCMF
36 - TTCLK
35 - ESCLK
34 - EECOPY
33 - ECS
32 - MOSI
31 - VCC
30 - GND
29 - MISO
28 - MTTCLK
27 - LOCK
26 - RTA4
25 - RTA3
48 - Pin Plastic 6mm x 6mm
Chip-Scale Package (QFN)
See Section 26.1 on page 250 for 48-Pin PQFP Configuration
DS6138 Rev. E
HOLT INTEGRATED CIRCUITS
www.holtic.com
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HI-6138
11.5. Bus Controller (BC) Time To Next Message Register (0x0036)................................. 87
11.6. Bus Controller (BC) Condition Code Register (Read 0x0037)................................... 87
11.7. Bus Controller (BC) General Purpose Flag Register (Write 0x0037)......................... 90
11.8. Bus Controller (BC) General Purpose Queue Pointer Register (0x0038).................. 90
11.9. Bus Controller (BC) Time Tag Counter (0x0043)....................................................... 91
11.10. Bus Controller (BC) Time Tag Counter High (0x0044)............................................... 91
11.11. Bus Controller (BC) Time Tag Utility Register (0x0045) ............................................ 92
11.12. Bus Controller (BC) Time Tag Utility High Register (0x0046) ................................... 92
11.13. Bus Controller (BC) Time Tag Match Register (0x0047) ........................................... 92
11.14. Bus Controller (BC) Time Tag Match High Register (0x0048) .................................. 92
11.15. Bus Controller Interrupt Registers and Their Use...................................................... 92
11.15.1. Bus Controller (BC) Interrupt Enable Register (0x0010) ....................................... 94
11.15.2. Bus Controller (BC) Pending Interrupt Register (0x0007) ..................................... 94
11.15.3. Bus Controller (BC) Interrupt Output Enable Register (0x0014) ........................... 94
12. SIMPLE MONITOR TERMINAL (SMT)............................................................. 97
12.1. Overview.................................................................................................................... 97
12.2. SMT Block Status Word (BSW) Description............................................................ 102
12.3. SMT Message Filter Table....................................................................................... 105
13. SIMPLE MONITOR TERMINAL (SMT) REGISTER DESCRIPTION.............. 107
13.1. SMT Configuration Register (0x0029)..................................................................... 107
13.2. SMT Bus Monitor Address List Start Address Register (0x002F)............................ 110
13.3. SMT Next Message Command Buffer Address (0x0030)........................................ 110
13.4. SMT Last Message Command Buffer Address (0x0031)..........................................111
13.5. SMT Bus Monitor Time Tag Count Register (0x003A)..............................................111
13.6. SMT Bus Monitor Time Tag Count Mid Register (0x003B).......................................111
13.7. SMT Bus Monitor Time Tag Count High Register (0x003C)......................................111
13.8. SMT Bus Monitor Time Tag Utility Register (0x003D).............................................. 112
13.9. SMT Bus Monitor Time Tag Utility Mid Register (0x003E)....................................... 112
13.10. SMT Bus Monitor Time Tag Utility High Register (0x003F)...................................... 112
13.11. SMT Bus Monitor Time Tag Match Register (0x0040)............................................. 113
13.12. SMT Bus Monitor Time Tag Match Mid Register (0x0041) ...................................... 113
13.13. SMT Bus Monitor Time Tag Match High Register (0x0042) .................................... 113
13.14. SMT Bus Monitor Interrupt Registers and Their Use............................................... 114
13.14.1. SMT Bus Monitor Interrupt Enable Register (0x0011).......................................... 115
HOLT INTEGRATED CIRCUITS
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HI-6138
List of Figures
Figure 1. Block Diagram............................................................................................................... 14
Figure 2. Address Mapping for Registers and RAM..................................................................... 19
Figure 3. Fixed Address Mapping for Interrupt Log Buffer............................................................ 39
Figure 4. Bus Controller Message Sequence Structures............................................................. 54
Figure 5. Bus Controller Flag Operation....................................................................................... 65
Figure 6. Structure of Bus Controller Message Control / Status Blocks in RAM.......................... 67
Figure 7. Simple Monitor Terminal (SMT) Data Storage............................................................. 101
Figure 8. Deriving the Monitor Filter Table Address from the Received Command Word.......... 105
Figure 9. MIL-STD-1553 Command Word Structure.................................................................. 135
Figure 10. Deriving the Illegalization Table Address From the Received Command Word........ 139
Figure 11. Address Mapping for Illegalization Table .................................................................. 140
Figure 12. Summary of RT Illegalization Table Addresses for Mode Code Commands ............ 141
Figure 13. Address Mapping for RT Descriptor Table ................................................................ 144
Figure 14. Deriving a Descriptor Table Control Word Address From Command Word .............. 145
Figure 15. Illustration of Ping-Pong Buffer Mode ....................................................................... 169
Figure 16. Ping-Pong Buffer Mode Example for a Receive Subaddress ................................... 171
Figure 17. Illustration of Indexed Buffer Mode ........................................................................... 174
Figure 18. Indexed Buffer Mode Example for a Receive Subaddress (broadcast disabled) ..... 175
Figure 19. Illustration of Circular Buffer Mode 1......................................................................... 178
Figure 20. Circular Buffer Mode 1 Example for a Receive Subaddress .................................... 179
Figure 21. Illustration of Circular Buffer Mode 2......................................................................... 183
Figure 22. Circular Buffer Mode 2 Example for a Receive Subaddress .................................... 184
Figure 23. Generalized Single-Byte Transfer Using SPI Protocol.
SCK is Shown for SPI Modes 0 and 3 ...................................................................... 208
Figure 24. Single-Word (2-Byte) Read From RAM or a Register............................................... 210
Figure 25. Single-Word (2-Byte) Write To RAM or a Register ....................................................211
HOLT INTEGRATED CIRCUITS
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