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PDF HI-3593 Data sheet ( Hoja de datos )
| Número de pieza | HI-3593 | |
| Descripción | 3.3V ARINC 429 Dual Receiver / Single Transmitter | |
| Fabricantes | HOLTIC | |
| Logotipo |  |
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August 2013
HI-3593
3.3V ARINC 429 Dual Receiver,
Single Transmitter with SPI Interface
GENERAL DESCRIPTION
PIN CONFIGURATIONS (Top View)
The HI-3593 from Holt Integrated Circuits is a CMOS
integrated circuit for interfacing a Serial Peripheral
Interface (SPI) enabled microcontroller to the ARINC 429
serial bus. The device provides two receivers, each with
user-programmable label recognition for any combination
of 256 possible labels, 32 x 32 Receive FIFO, 3 priority-
label quick-access double-buffered registers and analog
line receiver. The independent transmitter has a 32 x 32
Transmit FIFO and built-in line driver. The line driver
operates from a single 3.3V supply and includes on-chip
DC/DC converter to generate the bipolar ARINC 429
differential voltage levels needed to directly drive the
ARINC 429 bus. The status of the transmit and receive
FIFOs and priority-label buffers can be monitored using
the programmable external interrupt pins, or by polling the
HI-3593 Status Registers. Other features include a
programmable option of data or parity in the 32nd bit, and
the ability to switch the bit-signifiance of ARINC 429 labels.
Pins are available with different input resistance and
output resistance values which provides flexibility when
using external lightning protection circuitry.
The Serial Peripheral Interface minimizes the number of
host interface signals resulting in a small footprint device
that can be interfaced to a wide range of industry-standard
microcontrollers supporting SPI. Alternatively, the SPI
signals may be controlled using just four general purpose
I/O port pins from a microcontroller or custom FPGA. The
SPI and all control signals are CMOS and TTL compatible
and support 3.3V operation.
The HI-3593 applies the ARINC 429 protocol to the
receivers and transmitter. ARINC 429 databus timing
comes from a 1 MHz clock input, or an internal counter can
derive it from higher clock frequencies having certain fixed
values, possibly the external host processor clock.
FEATURES
· ARINC 429 specification compliant
· Single 3.3V power supply
· On-chip analog line driver and receiver connect
directly to ARINC 429 bus
· Programmable label recognition for 256 labels
· 32 x 32 Receive FIFOs and Priority-Label buffers
· Independent data rates for Transmit and Receive
· 10MHz, four-wire Serial Peripheral Interface (SPI)
· Industrial & extended temperature ranges
-1
RIN1A-40 - 2
RIN1A - 3
RIN1B - 4
RIN1B-40 - 5
RIN2A-40 - 6
RIN2A - 7
RIN2B - 8
RIN2B-40 - 9
MR - 10
ACLK - 11
HI-3593PCI
HI-3593PCT
HI-3593PCM
33 - AMPA
32 - TXAOUT
31 - AMPB
30 - TXBOUT
29 -
28 - TFULL
27 - TEMPTY
26 - R1FLAG
25 - R1INT
24 - R2FLAG
23 - R2INT
44 - Pin Plastic 7mm x 7mm
Chip-Scale Package (QFN)
-1
RIN1A-40 - 2
RIN1A - 3
RIN1B - 4
RIN1B-40 - 5
RIN2A-40 - 6
RIN2A - 7
RIN2B - 8
RIN2B-40 - 9
MR - 10
ACLK - 11
HI-3593PQI
HI-3593PQT
HI-3593PQM
33 - AMPA
32 - TXAOUT
31 - AMPB
30 - TXBOUT
29 -
28 - TFULL
27 - TEMPTY
26 - R1FLAG
25 - R1INT
24 - R2FLAG
23 - R2INT
44 - Pin Plastic Quad Flat Pack (PQFP)
(DS3593 Rev. B)
HOLT INTEGRATED CIRCUITS
www.holtic.com
08/13
1 page  
REGISTER DESCRIPTIONS
HI-3593
RECEIVE CONTROL REGISTER
(Receiver 1 Write, SPI Op-code 0x10)
(Receiver 1 Read, SPI Op-code 0x94)
(Receiver 2 Write, SPI Op-code 0x24)
(Receiver 2 Read, SPI Op-code 0xB4)
76543210
MSB
LSB
Bit Name
7 RFLIP
6 SD9
5 SD10
4 SDON
3 PARITY
2 LABREC
1 PLON
0 RATE
R/W Default Description
R/W 0 Setting this bit reverses the bit order of the first 8 bits of each ARINC 429 message received.
See figure 1 for details.
R/W 0 If the receiver decoder is enable by setting the SDON bit to a “1”, then ARINC 429 message
bit 9 must match this bit for the message to be accepted.
R/W 0 If the receiver decoder is enable by setting the SDON bit to a “1”, then ARINC 429 message
bit 10 must match this bit for the message to be accepted.
R/W 0 If this bit is set, bits 9 and 10 of the received ARINC 429 message must match SD9 and SD10
R/W 0 Received word parity checking is enabled when this bit is set. If “0”, all 32 bits of the received
ARINC 429 word are stored without parity checking.
R/W 0 When “0”, all received messages are stored. If this bit is set, incoming ARINC message label
filtering is enabled. Only messages whose corresponding label filter table entry is set to a “1”
will be stored in the Receive FIFO.
R/W 0 Priority-Label Register enable. If PLON = “1” the three Priority-Label Registers are enabled
and received ARINC 429 messages with labels that match one of the three pre-programmed
values will be capured and stored in the corresponding Prioty-Label Mail Boxes. If PLON = “0”
the Priority-Label matching feature is turned off and no words are placed in the mail boxes.
R/W 0 If RATE is “0”, ARINC 429 high-speed data rate is selected. RATE = “1” selects low-speed
ARINC 429 data rate (high-speed / 8).
TRANSMIT CONTROL REGISTER
(Write, SPI Op-code 0x08)
(Read, SPI Op-code 0x84)
76543210
MSB
LSB
Bit Name
R/W Default Description
7 HIZ
R/W 0 Setting this bit puts the on-chip line driver outputs to a high-impedance state.
6 TFLIP
R/W 0 Setting this bit reverses the bit order of the first 8 bits of each ARINC 429 message transmitted.
See figure 1 for details.
5 TMODE
R/W 0 If TMODE is “0”, data in the transmit FIFO is sent to the ARINC 429 bus only upon receipt of an
SPI op-code 0x40, transmit enable, command. If TMODE is a “1”, data is sent as soon as it is
available.
4 SELFTEST R/W 0 Setting SELFTEST causes an internal connection to be made looping-back the transmitter
outputs to both receiver inputs for self-test purposes. When in self-test mode, the HI-3593
ignores data received on the two ARINC 429 receive channels and holds the on-chip line driver
outputs in the NULL state to prevent self-test data being transmitted to other receivers on the
bus.
3 ODDEVEN R/W 0 If the TPARITY bit is set, the transmitter inserts an odd parity bit if ODDEVEN = “0”, or an even if
ODDEVEN = “1”.
2 TPARITY
R/W 0 If TPARITY = “0”, no parity bit is inserted and the 32nd transmitted bit is data. When TPARITY is
a “1” a parity bit is substituted for bit 32 according to the ODDEVEN bit value.
1X
R/W 0 Not used.
0 RATE
R/W 0 If RATE is “0”, ARINC 429 high-speed data rate is selected. RATE = “1” selects low-speed
ARINC 429 data rate (high-speed / 8).
HOLT INTEGRATED CIRCUITS
5
5 Page 
HI-3593
FUNCTIONAL DESCRIPTION (cont.)
RECEIVED ARINC 429 WORD
TO FILTERS (S/D, LABEL, PRIORITY-LABEL)
DATA
PARITY
CHECK
32 BIT SHIFT REGISTER
ONES
NULL
ZEROS
SHIFT REGISTER
SHIFT REGISTER
SHIFT REGISTER
WORD GAP
TIMER
WORD
GAP
1MHz
END
SEQUENCE
START CONTROL
BIT
CLOCK
1MHz
ERROR
DETECTION
ERROR
1MHz
FIGURE 3. RECEIVER BLOCK DIAGRAM
BIT
COUNTER
AND
END OF
SEQUENCE
1MHz
EOS
32ND
BIT
NEW WORD
RECEIVE DATA FIFO
Following S/D Filtering, accepted ARINC 429 words are
conditionally stored in the Receive FIFO. If label filtering is
disabled, all words are stored. If label filtering is enabled, the
incoming ARINC429 word’s label byte value is checked against its
corresponding bit in the pre-programmed label look-up table. If the
bit is set to a “1” the word is stored in the FIFO. If the bit is a “0” the
word is not stored in the FIFO.
LABEL RECOGNITION
The user loads the 256-bit label look-up table to specify which 8-bit
incoming ARINC labels are stored in the Receive FIFO, and which
are not. Setting a “1” in the look-up table enables processing of
received ARINC words containing the corresponding label. A “0”
in the look-up table causes discard of received ARINC words
containing the label. The 256-bit look-up table is loaded using SPI
Op-Codes 0x14 (Receiver 1) and 0x28 (Receiver 2), as described
in Table 1. After the look-up table is initialized, the Control Register
bit LABREC must be set to enable label recognition.
All four bytes of the incoming ARINC429 word are stored in the
FIFO.
Table 3. defines the rules for Receive FIFO loading.
READING THE LABEL LOOK-UP TABLE
The contents of the Label Look-up table may be read via the SPI
interface using Op-Code 0x98 (Receiver 1) or 0xB8 (Receiver 2) as
described in Table 1.
RETRIEVING DATA
Each time a valid ARINC 429 word is loaded into the FIFO, the
Receive FIFO Status Register FFEMPTY, FFHALF and FFFULL bits
are updated. When the FIFO is EMPTY, the FFEMPTY bit is a “1” and
FFHALF and FFFULL are “0”. Once the first received and accepted
ARINC 429 word is loaded into the FIFO, FFEMPTY goes low. Each
received ARINC 429 word is retrieved via the SPI interface using SPI
Op-Code 0xA0 (Receiver 1) or 0xC0 (Receiver 2).
Up to 32 ARINC 429 words may be held in the Receive FIFO.
FFFULL goes high when the Receive FIFO is full. Failure to unload
the Receive FIFO when full causes additional valid ARINC 429
words to overwrite Receive FIFO location 32.
A FIFO half-full flag (FFHALF) is high whenever the Receive FIFO
contains 16 or more words. The FFHALF bit provides a useful
indicator to the host CPU that a sixteen word data retrieval routine
may be performed.
The FFEMPTY, FFHALF or FFFULL status bits can also be output on
the R1FLAG (Receiver 1) and R2FLAG (Receiver 2) pins. Flag /
Interrupt Assignment Register bits 5, 4, 1 and 0 select which flag
appears. Additionally, a FIFO not empty option may be programmed
for the R1FLAG / R2FLAG pins causing the pin to go high any time at
least one word is available in the FIFO.
HOLT INTEGRATED CIRCUITS
11
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet HI-3593.PDF ] | |
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