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PDF AD629 Data sheet ( Hoja de datos )

Número de pieza AD629
Descripción Difference Amplifier
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo




1. AD629






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No Preview Available ! AD629 Hoja de datos, Descripción, Manual

FEATURES
Improved replacement for: INA117P and INA117KU
±270 V common-mode voltage range
Input protection to
±500 V common mode
±500 V differential mode
Wide power supply range (±2.5 V to ±18 V)
±10 V output swing on ±12 V supply
1 mA maximum power supply current
HIGH ACCURACY DC PERFORMANCE
3 ppm maximum gain nonlinearity (AD629B)
20 μV/°C maximum offset drift (AD629A)
10 μV/°C maximum offset drift (AD629B)
10 ppm/°C maximum gain drift
EXCELLENT AC SPECIFICATIONS
77 dB minimum CMRR @ 500 Hz (AD629A)
86 dB minimum CMRR @ 500 Hz (AD629B)
500 kHz bandwidth
APPLICATIONS
High voltage current sensing
Battery cell voltage monitors
Power supply current monitors
Motor controls
Isolation
100
95
90
85
80
75
70
65
60
55
5020
100 1k
FREQUENCY (Hz)
10k
Figure 2. Common-Mode Rejection Ratio vs. Frequency
20k
High Common-Mode Voltage,
Difference Amplifier
AD629
FUNCTIONAL BLOCK DIAGRAM
REF(–) 1
–IN 2
+IN 3
21.1k
380k
380k
–VS 4 AD629
380k
20k
NC = NO CONNECT
Figure 1.
8 NC
7 +VS
6 OUTPUT
5 REF(+)
GENERAL DESCRIPTION
The AD629 is a difference amplifier with a very high input,
common-mode voltage range. It is a precision device that allows
the user to accurately measure differential signals in the
presence of high common-mode voltages up to ±270 V.
The AD629 can replace costly isolation amplifiers in
applications that do not require galvanic isolation. The device
operates over a ±270 V common-mode voltage range and has
inputs that are protected from common-mode or differential
mode transients up to ±500 V.
The AD629 has low offset, low offset drift, low gain error drift,
low common-mode rejection drift, and excellent CMRR over a
wide frequency range.
The AD629 is available in die and packaged form featuring
8-lead PDIP and 8-lead SOIC packages. For all packages
(including die) and grades, performance is guaranteed over
the industrial temperature range of −40°C to +85°C.
2mV/DIV
60V/DIV
–240
–120
0
120
COMMON-MODE VOLTAGE (V)
240
Figure 3. Error Voltage vs. Input Common-Mode Voltage
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©1999-2011 Analog Devices, Inc. All rights reserved.

1 page




AD629 pdf
AD629
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage, VS
Internal Power Dissipation1
8-Lead PDIP (N)
8-Lead SOIC (R)
Input Voltage Range, Continuous
Common-Mode and Differential, 10 sec
Output Short-Circuit Duration
Pin 1 and Pin 5
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 60 sec)
Rating
±18 V
See Figure 4
See Figure 4
±300 V
±500 V
Indefinite
–VS − 0.3 V to +VS + 0.3 V
150°C
−55°C to +125°C
−65°C to +150°C
300°C
1 Specification is for device in free air:
8-Lead PDIP, θJA = 100°C/W;
8-Lead SOIC, θJA = 155°C/W.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
2.0
TJ = 150°C
8-LEAD PDIP
1.5
1.0
8-LEAD SOIC
0.5
0
–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE (°C)
Figure 4. Maximum Power Dissipation vs. Temperature for SOIC and PDIP
1a 1b
2
7
Y
3
4 6b
6a
5a 5b
X
DIE SIZE: 1655µm (X) by 2465µm (Y)
Figure 5. Metallization Photograph
Table 3. Pin Pad Coordinates
Coordinates1
Pad Pin
XY
1a REF(−) −677 +1082
1b −534 +1084
2 −IN
3 +IN
4 −VS
5a REF(+)
5b
−661
−661
+680
+396
+538
+939
−658
−800
−1084
−1084
6a OUTPUT +681 −950
6b +681 −807
7 +VS
+680 +612
Description
For the die model, either
pad can be bonded because
1a and 1b are internally
shorted.
For the die model, either
pad can be bonded because
5a and 5b are internally
shorted.
For the die model, both
pads must be bonded
because 6a and 6b are not
internally shorted.
1 All coordinates are with respect to the center of the die.
ESD CAUTION
Rev. C | Page 4 of 16

5 Page





AD629 arduino
AD629
THEORY OF OPERATION
The AD629 is a unity gain, differential-to-single-ended
amplifier (diff amp) that can reject extremely high common-
mode signals (in excess of 270 V with 15 V supplies). It consists
of an operational amplifier (op amp) and a resistor network.
To achieve high common-mode voltage range, an internal
resistor divider (Pin 3 or Pin 5) attenuates the noninverting
signal by a factor of 20. Other internal resistors (Pin 1, Pin 2,
and the feedback resistor) restore the gain to provide a differential
gain of unity. The complete transfer function equals
VOUT = V (+IN) − V (−IN)
Laser wafer trimming provides resistor matching so that
common-mode signals are rejected while differential input
signals are amplified.
To reduce output drift, the op amp uses super beta transistors
in its input stage. The input offset current and its associated
temperature coefficient contribute no appreciable output
voltage offset or drift, which has the added benefit of reducing
voltage noise because the corner where 1/f noise becomes
dominant is below 5 Hz. To reduce the dependence of gain
accuracy on the op amp, the open-loop voltage gain of the op
amp exceeds 20 million, and the PSRR exceeds 140 dB.
REF(–) 1
–IN 2
+IN 3
21.1k
380k
380k
–VS 4 AD629
380k
20k
8 NC
7 +VS
6 OUTPUT
5 REF(+)
NC = NO CONNECT
Figure 31. Functional Block Diagram
Rev. C | Page 10 of 16

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