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PDF GAL20V8 Data sheet ( Hoja de datos )
| Número de pieza | GAL20V8 | |
| Descripción | High Performance E2CMOS PLD Generic Array Logic | |
| Fabricantes | Lattice Semiconductor | |
| Logotipo |  |
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GAL20V8
High Performance E2CMOS PLD
Generic Array Logic™
Features
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 5 ns Maximum Propagation Delay
— Fmax = 166 MHz
— 4 ns Maximum from Clock Input to Data Output
— UltraMOS® Advanced CMOS Technology
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
— 75mA Typ Icc on Low Power Device
— 45mA Typ Icc on Quarter Power Device
• ACTIVE PULL-UPS ON ALL PINS
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Also Emulates 24-pin PAL® Devices with Full Function/
Fuse Map/Parametric Compatibility
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
• LEAD-FREE PACKAGE OPTIONS
Description
Functional Block Diagram
I/CLK
I
I
I
IMUX
CLK
8 OLMC
8 OLMC
8 OLMC
I
8 OLMC
I
8 OLMC
I
8 OLMC
I
8 OLMC
I
I 8 OLMC
OE
I
IMUX
Pin Configuration
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I/OE
The GAL20V8C, at 5ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E2) floating gate technology to provide the highest speed
performance available in the PLD market. High speed erase times
(<100ms) allow the devices to be reprogrammed quickly and ef-
ficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configura-
tions possible with the GAL20V8 are the PAL architectures listed
in the table of the macrocell description section. GAL20V8 devices
are capable of emulating any of these PAL architectures with full
function/fuse map/parametric compatibility.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
PLCC
4
I5
2 28 26
25 I/O/Q
I I/O/Q
I7
NC
I9
GAL20V8
Top View
23 I/O/Q
NC
21 I/O/Q
I I/O/Q
I 11
19 I/O/Q
12 14 16 18
DIP
I/CLK 1
24 Vcc
II
I GAL
I/O/Q
I 20V8
I
I/O/Q
I/O/Q
I6
I/O/Q
I 18 I/O/Q
I I/O/Q
I I/O/Q
I I/O/Q
II
GND 12
13 I/OE
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2006
20v8_07
1
1 page  
Specifications GAL20V8
Registered Mode
In the Registered mode, macrocells are configured as dedicated Dedicated input or output functions can be implemented as sub-
registered outputs or as I/O functions.
sets of the I/O function.
Architecture configurations available in this mode are similar to the
common 20R8 and 20RP4 devices with various permutations of
polarity, I/O and register placement.
All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or I/
O. Up to eight registers or up to eight I/Os are possible in this mode.
Registered outputs have eight product terms per output. I/Os have
seven product terms per output.
The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product Term Disable (PTD) fuses, are shown
on the logic diagram on the following page.
CLK
DQ
XOR Q
OE
XOR
Registered Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this output configuration.
- Pin 1 controls common CLK for the registered outputs.
- Pin 13 controls common OE for the registered outputs.
- Pin 1 & Pin 13 are permanently configured as CLK &
OE for registered output configuration.
Combinatorial Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this output configuration.
- Pin 1 & Pin 13 are permanently configured as CLK &
OE for registered output configuration..
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
5
5 Page 
SpSepceifcicifaictaiotinosnsGGALA2L02V08VC8
Absolute Maximum Ratings(1)
Recommended Operating Conditions
Supply voltage VCC ...................................... –0.5 to +7V
Input voltage applied .......................... –2.5 to VCC +1.0V
Off-state output voltage applied ......... –2.5 to VCC +1.0V
Storage Temperature ................................ –65 to 150°C
Ambient Temperature with
Power Applied ........................................ –55 to 125°C
1.Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).
Commercial Devices:
Ambient Temperature (TA) ............................... 0 to 75°C
Supply voltage (VCC)
with Respect to Ground ..................... +4.75 to +5.25V
Industrial Devices:
Ambient Temperature (TA) ........................... –40 to 85°C
Supply voltage (VCC)
with Respect to Ground ..................... +4.50 to +5.50V
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL PARAMETER
CONDITION
MIN. TYP.3 MAX. UNITS
VIL Input Low Voltage
VIH Input High Voltage
IIL1 Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.)
IIH
Input or I/O High Leakage Current
3.5V ≤ VIN ≤ VCC
VOL
Output Low Voltage
IOL = MAX. Vin = VIL or VIH
VOH
Output High Voltage
IOH = MAX. Vin = VIL or VIH
IOL Low Level Output Current
IOH High Level Output Current
IOS2
Output Short Circuit Current
VCC = 5V VOUT = 0.5V TA= 25°C
COMMERCIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V
Supply Current
ftoggle = 15MHz Outputs Open
L -5/-7/-10
INDUSTRIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V
Supply Current
ftoggle = 15MHz Outputs Open
L-10
Vss – 0.5
2.0
—
—
—
2.4
—
—
–30
—
—
—
—
—
—
—
—
—
0.8
Vcc+1
–100
10
0.5
—
16
–3.2
–150
V
V
μA
μA
V
V
mA
mA
mA
— 75 115 mA
— 75 130 mA
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25 °C
11
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet GAL20V8.PDF ] | |
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