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PDF PALCE16V8 Data sheet ( Hoja de datos )
| Número de pieza | PALCE16V8 | |
| Descripción | Reprogrammable CMOS PAL Device | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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16V8
PALCE16V8
Flash Erasable,
Reprogrammable CMOS PAL® Device
Features
• Active pull-up on data input pins
• Low power version (16V8L)
— 55 mA max. commercial (10, 15, 25 ns)
— 65 mA max. industrial (10, 15, 25 ns)
— 65 mA military (15 and 25 ns)
• Standard version has low power
— 90 mA max. commercial (10, 15, 25 ns)
— 115 mA max. commercial (7 ns)
— 130 mA max. military/industrial (10, 15, 25 ns)
• CMOS Flash technology for electrical erasability and
reprogrammability
• PCI compliant
• User-programmable macrocell
— Output polarity control
— Individually selectable for registered or combinato-
rial operation
• Up to 16 input terms and 8 outputs
• 7.5 ns com’l version
5 ns tCO
5 ns tS
7.5 ns tPD
125-MHz state machine
• 10 ns military/industrial versions
7 ns tCO
10 ns tS
10 ns tPD
62-MHz state machine
• High reliability
— Proven Flash technology
— 100% programming and functional testing
Functional Description
The Cypress PALCE16V8 is a CMOS Flash Electrical Eras-
able second-generation programmable array logic device. It is
implemented with the familiar sum-of-product (AND-OR) logic
structure and the programmable macrocell.
Logic Block Diagram (PDIP/CDIP)
GND
I8
I7 I6
I5 I4
I3 I2 I1 CLK/I0
10 9 8 7 6 5 4 3 2 1
88
PROGRAMMABLE
AND ARRAY
(64 x 32)
88
8
88
8
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
11 12
OE/I9
I/O0
Pin Configurations
13 14 15 16
I/O1 I/O2 I/O3 I/O4
CLK/I0
I1
I2
I3
I4
I5
I6
I7
I8
GND
DIP
Top View
1 20
2 19
3 18
4 17
5 16
6 15
7 14
8 13
9 12
10 11
VCC
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
OE/I9
16V8–2
17 18
I/O5 I/O6
PLCC/LCC
Top View
19
I/O7
20
VCC 16V8–1
3 2 1 2019
I3 4
18
I4 5
17
I5 6
16
I6 7
15
I7 8
14
9 10111213
I/O6
I/O5
I/O4
I/O3
I/O2
16V8–3
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-03025 Rev. **
Revised September 3, 1998
1 page  
AC Test Loads and Waveforms
3.0V
GND
< 2 ns
ALL INPUT PULSES
90%
10%
90%
10%
< 2 ns
16V8–5
5V
OUTPUT
S1
R1
TEST POINT
R2 CL
16V8–6
PALCE16V8
Specification
tPD, tCO
tPZX, tEA
tPXZ, tER
S1
Closed
Z · H: Open
Z · L: Closed
H · Z: Open
L · Z: Closed
CL
50 pF
5 pF
Commercial
R1
200Ω
R2
390Ω
Military
R1
390Ω
R2
750Ω
Measured Output Value
1.5V
1.5V
H · Z: VOH – 0.5V
L · Z: VOL + 0.5V
Document #: 38-03025 Rev. **
Page 5 of 13
5 Page 
Package Diagrams (continued)
20-Lead Plastic Leaded Chip Carrier J61
PALCE16V8
20-Square Leadless Chip Carrier L61
51-85000-A
Document #: 38-03025 Rev. **
51-80049
Page 11 of 13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet PALCE16V8.PDF ] | |
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