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PDF PALCE16V8Z Data sheet ( Hoja de datos )
| Número de pieza | PALCE16V8Z | |
| Descripción | EE CMOS 20-Pin Universal Programmable Array Logic | |
| Fabricantes | Lattice Semiconductor | |
| Logotipo |  |
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PALCE16V8 COM’L:H-5/7/10/15/25, Q-10/15/25 IND:H-10/15/25, Q-20/25
PALCE16V8Z COM’L:-25
IND:-12/15/25
PALCE16V8 and PALCE16V8Z Families
EE CMOS (Zero-Power) 20-Pin Universal
Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
x Pin and function compatible with all 20-pin PAL® devices
x Electrically erasable CMOS technology provides reconfigurable logic and full testability
x High-speed CMOS technology
— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version
x Direct plug-in replacement for the PAL16R8 series
x Outputs programmable as registered or combinatorial in any combination
x Peripheral Component Interconnect (PCI) compliant
x Programmable output polarity
x Programmable enable/disable control
x Preloadable output registers for testability
x Automatic register reset on power up
x Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages
x Extensive third-party software and programmer support
x Fully tested for 100% programming and functional yields and high reliability
x 5-ns version utilizes a split leadframe for improved performance
GENERAL DESCRIPTION
The PALCE16V8 is an advanced PAL device built with low-power, high-speed, electrically-
erasable CMOS technology. It is functionally compatible with all 20-pin GAL devices. The
macrocells provide a universal device architecture. The PALCE16V8 will directly replace the
PAL16R8, with the exception of the PAL16C1.
The PALCE16V8Z provides zero standby power and high speed. At 30-µA maximum standby
current, the PALCE16V8Z allows battery-powered operation for an extended period.
The PALCE16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to
implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic
can always be reduced to sum-of-products form, taking advantage of the very wide input gates
available in PAL devices. The equations are programmed into the device through floating-gate
cells in the AND logic array that can be erased electrically.
The fixed OR array allows up to eight data product terms per output for logic functions. The
sum of these products feeds the output macrocell. Each macrocell can be programmed as
registered or combinatorial with an active-high or active-low output. The output configuration
is determined by two global bits and one local bit controlling four multiplexers in each
macrocell.
Publication# 16493 Rev: F
Amendment/0
Issue Date: September 2000
1 page  
Programmable Output Polarity
The polarity of each macrocell can be active-high or active-low, either to match output signal
needs or to reduce product terms. Programmable polarity allows Boolean expressions to be
written in their most compact form (true or inverted), and the output can still be of the desired
polarity. It can also save “DeMorganizing” efforts.
Selection is through a programmable bit SL1x which controls an exclusive-OR gate at the output
of the AND/OR logic. The output is active high if SL1x is 1 and active low if SL1x is 0.
PALCE16V8 and PALCE16V8Z Families
5
5 Page 
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . .-55°C to +125°C
Supply Voltage
with Respect to Ground . . . . . . . . . . -0.5 V to +7.0 V
DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (TA = 0°C to 75°C) . . . . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum Rat-
ings for extended periods may affect device reliability. Pro-
gramming conditions may differ.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA)
Operating in Free Air . . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
Parameter
Symbol
Parameter Description
Test Description
Min Max Unit
VOH Output HIGH Voltage
VOL Output LOW Voltage
VIH Input HIGH Voltage
IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min
IOL = 24 mA, VIN = VIH or VIL, VCC = Min
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
2.4
0.5
2.0
V
V
V
VIL Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8 V
IIH Input HIGH Leakage Current
IIL Input LOW Leakage Current
IOZH Off-State Output Leakage Current HIGH
IOZL
ISC
ICC (Static)
Off-State Output Leakage Current LOW
Output Short-Circuit Current
Supply Current for -5
ICC (Dynamic) Supply Current for -7
VIN = 5.25 V, VCC = Max (Note 2)
VIN = 0 V, VCC = Max (Note 2)
VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 2)
VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 2)
VOUT = 0.5 V, VCC = Max (Note 3)
Outputs Open (IOUT = 0 mA), VIN = 0 V
VCC = Max
Outputs Open (IOUT = 0 mA),
VCC = Max, f = 25 MHz
10 µA
–100 µA
10 µA
–100 µA
–30 –150 mA
125 mA
115 mA
Notes:
1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
PALCE16V8H-5/7 (Com’l)
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PALCE16V8Z.PDF ] | |
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