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PDF MAX11154 Data sheet ( Hoja de datos )
| Número de pieza | MAX11154 | |
| Descripción | SAR ADC | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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EVALUATION KIT AVAILABLE
MAX11154
18-Bit, 500ksps, 0 to 5V SAR ADC with
Internal Reference in TDFN
General Description
The MAX11154 18-bit, 500ksps, SAR ADC offers excellent
AC and DC performance with unipolar input range, small
size, and internal reference. The MAX11154 integrates an
optional internal reference and buffer, saving additional
cost and space.
This ADC typically achieves 93.8dB SNR and -105.8dB THD.
The device guarantees 18-bit no-missing codes and ±2
LSB INL (typ).
The MAX11154 communicates using an SPI-compatible
serial interface at 2.3V, 3V, 3.3V, or 5V logic. The serial
interface can be used to daisy-chain multiple ADCs for
multichannel applications and provides a busy indicator
option for simplified system synchronization and timing.
The MAX11154 is offered in a 12-pin, 3mm x 3mm,
TDFN package and is specified over the -40NC to +85NC
temperature range.
Applications
●● Data Acquisition Systems
●● Industrial Control Systems/Process Control
●● Medical Instrumentation
●● Automatic Test Equipment
Benefits and Features
●● High DC/AC Accuracy Improves Measurement Quality
• 18-Bit Resolution with No Missing Codes
• 500ksps Throughput Rates without Pipeline Delay/
Latency
• 93.8dB SNR and -105.8dB THD at 10kHz
• 1.7 LSBRMS Transition Noise
• ±0.6 LSB DNL (typ) and ±2 LSB INL (typ)
●● Highly Integrated ADC Saves Cost and Space
• ±7ppm/°C Internal Reference
• Internal Reference Buffer
●● Wide Supply Range and Low Power Simplify
Power-Supply Design
• 5V Analog Supply
• 2.3V to 5V Digital Supply
• 23.6mW Power Consumption with External Reference
at 500ksps
• 10µA in Shutdown Mode
●● Multi-Industry Standard Serial Interface and
Small Package Reduce Size
• SPI/QSPI™/MICROWIRE®/DSP-Compatible
Serial Interface
• 3mm x 3mm Tiny 12-Pin TDFN Package
Selector Guide and Ordering Information appear at end of
data sheet.
Typical Operating Circuit
0 to 5V
10Ω
MAX9632
4.7nF
AIN+
AIN-
REF
10µF
1µF VDD
(5V)
0.1µF
OVDD
(2.3V TO 5V)
18-BIT ADC
MAX11154
REF
BUF
INTERFACE
AND CONTROL
CONFIGURATION REGISTER
INTERNAL
REFERENCE
AGNDS
GND
SCLK
DIN
DOUT
HOST
CONTROLLER
CNVST
REFIO
0.1µF
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corporation.
14-Bit to 18-Bit SAR ADC Family
14-BIT
16-BIT
16-BIT 18-BIT
500ksps 250ksps 500ksps 500ksps
±5V Input
Internal
Reference
—
MAX11167
MAX11169
0 to 5V Input
Internal
Reference
—
MAX11161
MAX11165
0 to 5V Input
External MAX11262 MAX11163
Reference
MAX11166 MAX11156
MAX11168 MAX11158
MAX11160 MAX11150
MAX11164 MAX11154
MAX11162 MAX11152
19-6722; Rev 2; 11/15
1 page  
MAX11154
18-Bit, 500ksps, 0 to 5V SAR ADC with
Internal Reference in TDFN
Electrical Characteristics (continued)
(VDD = 4.75V to 5.25V, VOVDD = 2.3V to 5.25V, fSAMPLE = 500ksps, Reference Mode 3, VREF = 4.096V; TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25NC.) (Note 2)
PARAMETER
SCLK Period (CS Mode)
SCLK Period (Daisy-Chain Mode)
SCLK Low Time
SCLK High Time
SCLK Falling-Edge to Data Valid
Delay
CNVST Low to DOUT D15 MSB
Valid (CS Mode)
CNVST High or Last SCLK
Falling Edge to DOUT High
Impedance
SYMBOL
tSCLK
tSCLK
tSCLKL
tSCLKH
tDDO
tEN
tDIS
CONDITIONS
VOVDD > 4.5V
VOVDD > 2.7V
VOVDD > 2.3V
VOVDD > 4.5V
VOVDD > 2.7V
VOVDD > 2.3V
VOVDD > 4.5V
VOVDD > 2.7V
VOVDD > 2.3V
VOVDD > 2.7V
VOVDD < 2.7V
CS Mode
MIN TYP MAX UNITS
14
20 ns
26
16
24 ns
30
5 ns
5 ns
12
18 ns
23
14
ns
17
20 ns
DIN Valid Setup Time from SCLK
Falling Edge
DIN Valid Hold Time from SCLK
Falling Edge
tSDINSCK
VOVDD > 4.5V
VOVDD > 2.7V
VOVDD > 2.3V
tHDINSCK
3
5 ns
6
0 ns
SCLK Valid Setup Time to
CNVST Falling Edge
tSSCKCNF
3 ns
SCLK Valid Hold Time to CNVST
Falling Edge
tHSCKCNF
6 ns
Note 2: Maximum and minimum limits are fully production tested over specified supply voltage range and at a temperature of
+25°C. Limits over the operating temperature range are guaranteed by design and device characterization.
Note 3: See the Analog Inputs and Overvoltage Input Clamps sections.
Note 4: Static Performance limits are guaranteed by design and device characterization. For definitions, see the Definitions section.
Note 5: Defined as the change in positive full-scale code transition caused by a Q5% variation in the VDD supply voltage.
Note 6: 10kHz sine wave input, -0.1dB below full scale.
Note 7: See Table 4 for definition of the reference modes.
Note 8: fIN1 ~ 9.4kHz, fIN2 ~ 10.7kHz, Each tone at -6.1dB below full scale.
Note 9: CLOAD = 65pF on DOUT.
www.maximintegrated.com
Maxim Integrated │ 5
5 Page 
MAX11154
Pin Configuration
18-Bit, 500ksps, 0 to 5V SAR ADC with
Internal Reference in TDFN
TOP VIEW
REFIO 1
REF 2
VDD 3
AIN+ 4
AIN- 5
GND 6
MAX11154
EP
TDFN
12 AGNDS
11 OVDD
10 DIN
9 SCLK
8 DOUT
7 CNVST
Pin Description
PIN NAME
I/O
1
REFIO
I/O
2
REF
I/O
3 VDD I
4 AIN+
5 AIN-
6 GND
I
I
I
7 CNVST I
8 DOUT O
9 SCLK I
10 DIN
I
11 OVDD
I
12 AGNDS
I
— EP —
FUNCTION
External Reference Input/Internal Reference Output. Place a 0.1µF capacitor from REFIO to
AGNDS.
External Reference Input/Reference Buffer Decoupling. Bypass to AGNDS in close proximity with a
X5R or X7R 10µF 16V capacitor. See the Layout, Grounding, and Bypassing section.
Analog Power Supply. Bypass to GND with a 0.1µF capacitor for each device and one 10µF
capacitor per PCB.
Positive Analog Input
Negative Analog Input. Connect AIN- to the analog ground plane or to a remote-sense ground.
Power-Supply Ground
Convert Start Input. The rising edge of CNVST initiates conversions. The falling edge of CNVST
with SCLK high enables the serial interface.
Serial Data Output. DOUT will change state on the falling edge of SCLK.
Serial Clock Input. Clocks data out of the serial interface when the device is selected.
Serial Data Input. DIN data is latched into the serial interface on the rising edge of SCLK.
Digital Power Supply. Bypass to GND with a 0.1µF capacitor for each device and one 10µF
capacitor per PCB.
Analog Ground Sense. Zero current reference for the on-board DAC and reference source.
Reference for REFIO and REF.
Exposed Pad. Connect to PCB GND.
www.maximintegrated.com
Maxim Integrated │ 11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet MAX11154.PDF ] | |
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