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PDF DS2450 Data sheet ( Hoja de datos )
| Número de pieza | DS2450 | |
| Descripción | 1-Wire Quad A/D Converter | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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AVAILABLE
DS2450
1-Wire Quad A/D Converter
FEATURES
Four high-impedance inputs to measure
analog voltages over the 1-Wire® bus
User programmable input range (2.56V,
5.12V), resolution (1 to 16 bits) and alarm
thresholds
5V, single supply operation
Very low power: 2.5 mW active, 25 μW idle
Built-in multidrop controller allows multiple
DS2450’s to be identified and operated on a
common 1-Wire bus
Responds to Conditional Search if the analog
voltage crosses the alarm thresholds
Channels not used as analog input can serve
as open drain digital outputs for closed-loop
control
Directly connects to a single port pin of a
microprocessor and communicates at up to
16.3k bits per second
Overdrive mode boosts communication speed
to 142k bits per second
On-chip 16-bit CRC-generator for
safeguarding data Ftraunnsfcertsional Diagrams
Unique, factory-lasered and tested 64-bit
registration number (8-bit family code + 48-
bit serial number 8-bit CRC tester) assures
absolute traceability because no two parts are
alike
8-bit family code specifies device
communication requirements to bus master
Operating temperature range from -40°C to
+85°C
Compact, low cost 8-pin SOIC surface mount
package
PIN ASSIGNMENT
VCC 1 8 AIN-D
NC 2 7 AIN-C
DATA 3 6 AIN-B
GND 4 5 AIN-A
8-PIN SOIC (208 MIL)
PIN DESCRIPTION
VCC 4.5 to 5.5V
NC Do Not Connect
DATA
1-Wire Bus
GND
Ground
AIN-A
Analog Input A
AIN-B
Analog Input B
AIN-C
Analog Input C
AIN-D
Analog Input D
ORDERING INFORMATION
DS2450S
8-pin SOIC
DS2450S/T&R
8-pin SOIC Tape-and-Reel
DS2450S+
8-pin SOIC
DS2450S+T&R
8-pin SOIC Tape-and-Reel
+ Indicates lead-free compliance.
1-Wire is a registered trademark of Dallas Semiconductor.
DESCRIPTION
The DS2450 1-Wire Quad A/D Converter is based on a successive-approximation analog to digital
coFPnuivnneCcrtotioennrfiagwluDriaitathigoranasmfaospucporenattroinauoteendnedataoenfndadalotoagf sdhmaetaeutsl.thiepelte. xer. Each input channel has its own register set to store the
inpUuCtSPvoislatatrgaedermaanrgk eof, MreaxsiomluInttieognra,teadnPdroadluacrtsm, Intch.reshold values as well as flags to enable participation of the
device in the conditional search if the input voltage leaves the specified range. Two alarm flags for each
channel indicate if the voltage measured was too high or too low without requiring the bus master to do
For pricing, delivery, and ordering information, opfl2e4ase contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
112706
1 page  
DS2450
The next bits, OC (output control) and OE (enable output) control the alternate use of a channel as output.
For normal operation as analog input the OE bit of a channel needs to be 0, rendering the OC bit to a
don’t care. With OE set to 1, a 0 for OC will make the channel’s output transistor conducting, a 1 for OC
will switch the transistor off. With a pullup resistor to a positive voltage, for example, the OC bit will
directly translate into the voltage equivalent of its logic state. Enabling the output does not disable the
analog input. Conversions remain possible, but will result in values close to 0 if the transistor is
conducting.
The IR bit in the second byte of a channel’s control and status memory selects the input voltage range.
With IR set to 0, the highest possible conversion result is reached at 2.55V. Setting IR to 1 requires an
input voltage of 5.10V for the same result. The next bit beyond IR has no function. It will always read 0
and cannot be changed to 1.
The next two bits, AEL alarm enable low and AEH alarm enable high, control whether the device will
respond to the Conditional Search command (see ROM Functions) if a conversion results in a value
higher (AEH) than or lower (AEL) than the channel’s alarm threshold voltage as specified in the alarm
settings. The alarm flags AFL (low) and AFH (high) tell the bus master whether the channel’s input
voltage was beyond the low or high threshold at the latest conversion. These flags are cleared
automatically if a new conversion reveals a non-alarming value. They can alternatively be written to 0 by
the bus master without a conversion.
The next bit of a channel’s control and status memory always reads 0 and cannot be changed to 1. The
POR bit (power on reset) is automatically set to 1 as the device performs a power-on reset cycle. As long
as this bit is set the device will always respond to the Conditional Search command in order to notify the
bus master that the control and threshold data is no longer valid. After powering-up the POR bit needs to
be written to 0 by the bus master. This may be done together with restoring the control and threshold
data. It is possible for the bus master to write the POR bit to a 1. This will make the device participate in
the conditional search but will not generate a reset cycle. Since the POR bit is related to the device and
not channel-specific the value written with the most recent setting of an input range or alarm enable
applies. The power-on default setting for the control/status data is 08h for the first and 8Ch for the
second byte of each channel.
MEMORY MAP PAGE 1, CONTROL/STATUS DATA Figure 5b
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2
08
OE-A
OC-A
0
0 RC3-A RC2-A
09 POR
0 AFH-A AFL-A AEH-A AEL-A
0A
OE-B
OC-B
0
0 RC3-B RC2-B
0B POR
0 AFH-B AFL-B AEH-B AEL-B
0C
OE-C
OC-C
0
0 RC3-C RC2-C
0D POR
0 AFH-C AFL-C AEH-C AEL-C
0E
OE-D
OC-D
0
0 RC3-D RC2-D
0F POR
0 AFH-D AFL-D AEH-D AEL-D
bit 1
RC1-A
0
RC1-B
0
RC1-C
0
RC1-D
0
bit 0
RC0-A
IR-A
RC0-B
IR-B
RC0-C
IR-C
RC0-D
IR-D
5 of 24
5 Page 
DS2450
With VCC power supply the bus master may either send a reset pulse to exit the Convert command or
continuously generate read data time slots. As long as the DS2450 is busy with conversions the bus
master will read 0’s. After the conversion is completed the bus master will receive 1’s instead. Since in a
open-drain environment a single 0 overwrites multiple 1’s the bus master can monitor multiple devices
converting simultaneously and immediately knows when the last one is ready. As in the parasitically
powered scenario the bus master finally has to exit the Convert command by issuing a rest pulse.
1-WIRE BUS SYSTEM
The 1-Wire bus is a system which has a single bus master and one or more slaves. In all instances the
DS2450 is a slave device. The discussion of this bus system is broken down into three topics: hardware
configuration, transaction sequence, and 1-Wire signaling (signal types and timing). A 1-Wire protocol
defines bus transactions in terms of the bus state during specific time slots that are initiated on the falling
edge of sync pulses from the bus master. For a more detailed protocol description, refer to Chapter 4 of
the Book of DS19xx iButton Standards.
HARDWARE CONFIGURATION
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to
drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open
drain or 3-state outputs. The 1-Wire port of the DS2450 is open drain with an internal circuit equivalent
to that shown in Figure 8. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. At
regular speed the 1-Wire bus has a maximum data rate of 16.3k bits per second. The speed can be
boosted to 142k bits per second by activating the Overdrive Mode. The 1-Wire bus requires a pullup
resistor of approximately 5kΩ at regular speed or maximum 2.2kΩ at Overdrive speed for
communication. During A/D conversions the bus master must provide a strong pullup to 5V to supply
sufficient energy if the DS2450 is powered entirely from the 1-Wire bus.
The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus
MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low
for more than 16 μs (Overdrive Speed) or more than 120 μs (regular speed), one or more devices on the
bus may be reset.
HARDWARE CONFIGURATION Figure 8
SEE TEXT
11 of 24
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet DS2450.PDF ] | |
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