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PDF DS28E17 Data sheet ( Hoja de datos )
| Número de pieza | DS28E17 | |
| Descripción | 1-Wire-to-I2C Master Bridge | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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DS28E17
1-Wire-to-I2C Master Bridge
General Description
The DS28E17 is a 1-Wire slave to I2C master bridge
device that interfaces directly to I2C slaves at standard
(100kHz max) or fast (400kHz max). Data transfers seri-
ally by means of the 1-Wire® protocol, which requires only
a single data lead and a ground return. Every DS28E17
is guaranteed to have a unique 64-bit ROM registration
number that serves as a node address in the 1-Wire net-
work. Multiple DS28E17 devices can coexist with other
devices in the 1-Wire network and be accessed individu-
ally without affecting other devices. The DS28E17 allows
using complex I2C devices such as display controllers,
ADCs, DACs, I2C sensors, etc. in a 1-Wire environment.
Each self-timed DS28E17 provides 1-Wire access for a
single I2C interface.
Applications
●● Accessory Identification and Control
●● I2C Sensors
●● Display Controllers
●● ADCs/DACs
Ordering Information appears at end of data sheet.
Typical Operating Circuit
Benefits and Features
●● Converts 1-Wire Communication Protocol to I2C
Master I/O
• Operates I2C Slave Peripherals over the Single-
Contact, 1-Wire Interface
●● Flexible 1-Wire Slave and I2C Master Operational
Modes
• Supports 15kbps and 77kbps 1-Wire Protocol with
Packetized I2C Data Payloads
• Factory-Programmed, Unique 64-Bit 1-Wire ROM
ID Provides Unalterable Serial Number to End
Equipment
• Standard 100kHz and 400kHz Communication
Rates for I2C
• I2C Clock Stretching Automatically Supported
●● Low Power Consumption
• 0.3µA (typ) in Sleep Mode
• 2.6mA (typ) when Operational
• Separate Pins for Sleep and Wakeup Flexibility
• Remote Power Controlled by an Awake Pin
• Sleep Mode Enabled by Sleep Pin or a 1-Wire
Device Command
●● Easy to Integrate
• 3.3V(nom) Supply, Small 4mm x 4mm x 0.75mm
TQFN package, -40°C to +85°C Operation
• Evaluation HW and SW Available
VDD VDD
VDD
GPIO
µC
RPUP
VDD
RESET
SCL
IO
SDA
AWAKE
DS28E17
WAKEUP BUSY
SLEEP
XD
ED REG18
GND
VDD
SCL
SDA
SLP_N
I2C SLAVE
GND
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
19-7681; Rev 0; 7/15
1 page  
DS28E17
1-Wire-to-I2C Master Bridge
Electrical Characteristics (continued)
(TA = -40°C to +85°C, VDD = VPUP, unless otherwise noted.) (Note 2)
SDA/SCL Rise Time
tR_I2C
Standard mode
Fast mode
Setup Time for STOP
Bus Free Time Between
STOP and START
Capacitive Load for Each
Bus Line
Noise Margin at the Low
Level for Each Connected
Device (Including
Hysteresis)
tSU:STO
tBUF
CB
Standard mode
Fast mode
Standard mode
Fast mode
VnL_I2C
Noise Margin at the High
Level for Each Connected
Device (Including
Hysteresis)
VnH_I2C
20 +
0.1CB
4.0
0.6
4.7
1.3
0.1 x
VDD
0.2 x
VDD
1000
300
400
ns
µs
µs
pF
V
V
Note 2: Limits are 100% production tested at TA = +25°C and TA = +70°C. Limits over the operating temperature range and rel-
evant supply voltage range are guaranteed by design and characterization. Typical values are at TA = +25°C.
Note 3: System requirement.
Note 4: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery
times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. The
pullup resistance power should be applied at the same time or after VDD to minimize back charging.
Note 5: Guaranteed by design and/or characterization only. Not production tested.
Note 6: Voltage below which, during a falling edge on IO, a logic-zero is detected.
Note 7: The voltage on IO must be less than or equal to VILMAX at all times the master is driving IO to a logic-zero level.
Note 8: Voltage above which, during a rising edge on IO, a logic-one is detected.
Note 9: Applies to a single device attached to a 1-Wire line.
Note 10: Defines maximum possible bit rate. Equal to 1/(tW0LMIN + tRECMIN).
Note 11: Interval after tRSTL during which a bus master can read a logic 0 on IO if there is a DS28E17 present. The power-up pres-
ence detect pulse could be outside this interval but will be complete within 2ms after power-up.
Note 12: ε in Figure 5 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VIH. The actual
maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively.
Note 13: δ in Figure 6 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high
threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.
www.maximintegrated.com
Maxim Integrated │ 5
5 Page 
DS28E17
1-Wire-to-I2C Master Bridge
TO FIGURE 4A
FROM FIGURE 4A
A5H
RESUME
COMMAND?
Y
N
3CH
OVERDRIVE
SKIP ROM?
Y
RC = 0 ; OD = 1
N
69H
OVERDRIVE MATCH
ROM?
N
Y
RC = 0 ; OD = 1
FROM FIGURE 4A
MASTER
Tx RESET ?
N
Y
RC = 1 ?
Y
N
MASTER
Tx RESET ?
N
Y
MASTER Tx BIT 0
BIT 0
MATCH?
Y
MASTER Tx BIT 1
N 1)
OD = 0
BIT 1
MATCH?
Y
1)
N
OD = 0
MASTER Tx BIT 63
BIT 63
MATCH?
Y
N
1)
OD = 0
RC = 1
TO FIGURE 4A
1) THE OD FLAG REMAINS AT 1 IF THE DEVICE WAS ALREADY AT OVERDRIVE SPEED BEFORE THE
OVERDRIVE MATCH ROM COMMAND WAS ISSUED.
Figure 4b. ROM Functions Flow Chart (continued)
www.maximintegrated.com
Maxim Integrated │ 11
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet DS28E17.PDF ] | |
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