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PDF DS2433 Data sheet ( Hoja de datos )
| Número de pieza | DS2433 | |
| Descripción | 4Kb 1-Wire EEPROM | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de DS2433 (archivo pdf) en la parte inferior de esta página. Total 23 Páginas | ||
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AVAILABLE
DS2433
4Kb 1-Wire EEPROM
FEATURES
4096 Bits Electrically Erasable Programmable
Read-Only Memory (EEPROM)
Unique, Factory-Lasered and Tested 64-Bit
Registration Number (8-Bit Family Code +
48-Bit Serial Number + 8-Bit CRC Tester)
Assures Absolute Identity Because No Two
Parts Are Alike
Built-In Multidrop Controller Ensures
Compatibility with Other MicroLAN
Products
Memory Partitioned Into Sixteen 256-Bit
Pages for Packetizing Data
256-Bit Scratchpad with Strict Read/Write
Protocols Ensures Integrity of Data Transfer
Reduces Control, Address, Data, and Power
to a Single Data Pin
Directly Connects to a Single Port Pin of a
Microprocessor and Communicates at Up to
16.3kbps
Overdrive Mode Boosts Communication
Speed to 142kbps
8-Bit Family Code Specifies DS2433
Communication RFequunircemtieontnsatol RDeiaadegrrams
Presence Detector Acknowledges When
Reader First Applies Voltage
Low-Cost PR-35, SFN, Flip Chip, or 8-Pin
SO Surface-Mount Packages
Reads and Writes Over a Wide Voltage
Range of 2.8V to 6.0V from -40°C to +85°C
PIN DESCRIPTION
PIN PR-35 SO
SFN
Flip
Chip
1 Ground NC
Data Ground
2 Data NC Ground Data
3
NC Data
—
NC
4 — Ground — NC
5P,in6Configur—ations appeaNr Cat end of da—ta sheet. NC
7FU,uCn8ScPtiiosnaatlrDad—iaegmraamrksofcMonaNtxiniCmueIndteagt reantedd—oPfrdoadtuacstsh, eInect—..
PIN CONFIGURATIONS
TOP VIEW
NC
NC
DATA
GND
1 8 NC
2 7 NC
3 6 NC
4 5 NC
SO (208 mils)
123
12 3
BOTTOM VIEW
PR-35
Pin Configurations continued at end of data sheet.
ORDERING INFORMATION
PART
TEMP RANGE PIN-PACKAGE
DS2433+
-40°C to +85°C 3 PR-35
DS2433S+
-40°C to +85°C 8 SO
DS2433S+T&R -40°C to +85°C 8 SO
DS2433G+T&R -40°C to +85°C 2 SFN
DS2433X#T
-40°C to +85°C
6 Flip Chip
(10k pieces)
DS2433X-S#T -40°C to +85°C
6 Flip Chip
(2.5k pieces)
+Denotes a lead(Pb)-free package.
#Denotes a RoHS-compliant device that may include lead(Pb) that is
exempt under the RoHS requirements.
T/T&R = Tape and reel.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
P1R9E-5L5IM81IN; 1A0R/1Y0
1 page  
Figure 2. HIERARCHCAL STRUCTURE FOR 1-Wire PROTOCOL
DS2433
Figure 3. 64-BIT LASERED ROM
MSB
LSB
8-BIT CRC CODE
48-BIT SERIAL NUMBER 8-BIT FAMILY CODE (23h)
MSB
LSB MSB
LSB MSB
LSB
Figure 4. 1-Wire CRC GENERATOR
Polynomial = X8 + X5 + X4 + 1
1st 2nd 3rd 4th
STAGE STAGE STAGE STAGE
X0 X1 X2 X3
5th
STAGE
X4
5 of 23
6th 7th 8th
STAGE STAGE STAGE
X5 X6
X7
INPUT DATA
X8
5 Page 
Figure 8. HARDWARE CONFIGURATION
RPU*
DS2433
*5k IS ADEQUATE FOR READING THE DS2433. TO WRITE TO A SINGLE DEVICE, A 2.2k RESISTOR AND VPUP OF AT LEAST 4.0V IS
SUFFICIENT. FOR WRITING MULTIPLE DS2433s SIMULTANEOUSLY OR OPERATION AT LOW VPUP, THE RPU SHOULD BE BYPASSED
BY A LOW-IMPEDANCE PULLUP TO VPUP WHILE THE DEVICE COPIES THE SCRATCHPAD TO EEPROM. DEPENDING ON THE 1-Wire
COMMUNICATION SPEED AND THE BUS LOAD CHARACTERISTICS, THE OPTIMAL PULLUP RESISTOR (RPU) VALUE WILL BE IN THE
1.5k TO 5k RANGE.
1-Wire BUS SYSTEM
The 1-Wire bus is a system which has a single bus master and one or more slaves. In all instances the
DS2433 is a slave device. The bus master is typically a microcontroller. The discussion of this bus system
is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling
(signal types and timing). A 1-Wire protocol defines bus transactions in terms of the bus state during
specific time slots that are initiated on the falling edge of sync pulses from the bus master.
HARDWARE CONFIGURATION
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to
drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open
drain or 3-state outputs. The 1-Wire port of the DS2433 is open drain with an internal circuit equivalent
to that shown in Figure 8. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. At
regular speed the 1-Wire bus has a maximum data rate of 16.3kbps. The speed can be boosted to 142kbps
by activating the Overdrive Mode. The 1-Wire bus requires a pullup resistor of approximately 5k.
The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus
MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low
for more than 16s (Overdrive Speed) or more than 120s (regular speed), one or more devices on the
bus may be reset.
TRANSACTION SEQUENCE
The protocol for accessing the DS2433 via the 1-Wire port is as follows:
Initialization
ROM Function Command
Memory Function Command
Transaction/Data
11 of 23
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet DS2433.PDF ] | |
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