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PDF ICS932S202 Data sheet ( Hoja de datos )
| Número de pieza | ICS932S202 | |
| Descripción | Frequency Timing Generator | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS932S202
Frequency Timing Generator for Differential PIII Type
Dual-CPU Systems
Recommended Application:
Serverwork HE-T, HE-SL & LE-T Chipsets
Output Features:
• 2 - CPUs @ 2.5V, up to 180MHz
• 2 - CPU chipset @ 2.5V, up to 180MHz
• 3 - IOAPIC @ 2.5V
• 3 - 3V66MHz @ 3.3V
• 11 - PCIs @ 3.3V
• 1 - 48MHz, @ 3.3V fixed
• 1 - 24/48MHz, @ 3.3V
• 2 - REF @ 3.3V
Features:
• Up to 180MHz frequency support
• Support power management: Power down Mode
from I2C programming.
• Spread spectrum for EMI control
± 0.25% center spread).
• Uses external 14.318MHz crystal
• 5 - FS pins for frequency select
Key Specifications:
• CPU Output Jitter: <150ps
• IOAPIC Output Jitter: <500ps
• 48MHz, 3V66, PCI Output Jitter: <500ps
• Ref Output Jitter. <1000ps
• CPU Output Skew: <175ps
• IOAPIC Output Skew <250ps
• PCI Output Skew: <500ps
• 3V66 Output Skew <250ps
• CPU to 3V66 Output Offset: 0.8 - 1.8ns (typ =
1.3ns)
• CPU to PCI Output Offset: 0.0 - 1.5ns (typ =
0.9ns)
• CPU to IOAPIC Output Offset: 1.5 - 4.0ns (typ =
2.0ns)
Block Diagram
PLL2
X1 XTAL
X2 OSC
PLL1
Spread
Spectrum
SEL24_48#
SDATA
SCLK
FS (4:0)
PD#
Control
Logic
Config.
Reg.
/2
CPU
DIVDER
IOAPIC
DIVDER
PCI
DIVDER
3V66
DIVDER
0600A—08/04/03
48MHz
24_48MHz
REF (1:0)
CPUCLK (1:0)
CPU_CSCLK (1:0)
IOAPIC (2:0)
PCICLK (10:0)
3V66 (2:0)
Pin Configuration
GNDREF
REF0
*SEL24_48#/REF1
VDDREF
X1
X2
GNDPCI
*FS0/PCICLK0
*FS1/PCICLK1
VDDPCI
*FS2/PCICLK2
*FS3/PCICLK3
GNDPCI
PCICLK4
PCICLK5
VDDPCI
PCICLK6
PCICLK7
GNDPCI
PCICLK8
PCICLK9
PCICLK10
VDDPCI
PD#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDLAPIC
47 IOAPIC0
46 IOAPIC1
45 GNDLAPIC
44 IOAPIC2
43 VDDLCPU
42 CPUCLK0
41 GNDLCPU
40 CPUCLK1
39 VDDLCPU
38 CPU_CSCLK0
37 CPU_CSCLK1
36 GNDLCPU
35 VDD66
34 3V66_0
33 3V66_1
32 3V66_2
31 GND66
30 SDATA
29 SCLK
28 VDD48
27 48MHz/FS4*
26 24_48MHz
25 GND48
48-pin SSOP
*120K ohm pull-up to VDD on indicated inputs.
1 page  
ICS932S202
Byte 1: CPU, Active/Inactive
Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
40
38
37
42
47
46
44
-
PWD
1
1
1
1
1
1
1
X
Description
CPUCLK 1
CPUCSCLK0
CPUCSCLK1
CPUCLK 0
IOAPIC0
IOAPIC1
IOAPIC2
(Reserved)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 2: PCI Active/Inactive
Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Pin # PWD
Description
18 1 PCICLK7
17 1 PCICLK6
Bit 5
Bit 4
Bit 3
15
14
12
1 PCICLK5
1 PCICLK4
1 PCICLK3
Bit 2
Bit 1
11
9
1 PCICLK2
1 PCICLK1
Bit 0 8
1 PCICLK0
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 3: 3V66 Active/Inactive Register
(1 = enable, 0 = disable)
Byte 4: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
34
33
32
-
2
3
-
-
PWD
1
1
1
X
1
1
X
X
Description
3V66_0
3V66_1
3V66_2
FS1#
REF0
REF1
FS3#
FS2#
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
26
27
-
-
22
21
20
-
PWD
1
1
X
1
1
1
1
X
Description
24_48MHz
48MHz
FS0#
(Reserved)
PCICLK10
PCICLK9
PCICLK8
FS4#
Notes:
1. Inactive means outputs are held LOW and are
disabled from switching.
Byte 5: Active/Inactive Register
(1= enable, 0 = disable)
Bit Pin # PWD
Description
Bit7 -
1 Reserved (Note)
Bit6 -
1 Reserved (Note)
Bit5 -
1 Reserved (Note)
Bit4 -
1 Reserved (Note)
Bit3 -
1 Reserved (Note)
Bit2 -
1 Reserved (Note)
Bit1 -
1 Reserved (Note)
Bit0 -
1 Reserved (Note)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte6: Active/Inactive Register
(1= enable, 0 = disable)
Bit Pin # PWD
Description
Bit7 -
0 Reserved (Note)
Bit6 -
0 Reserved (Note)
Bit5 -
0 Reserved (Note)
Bit4 -
0 Reserved (Note)
Bit3 -
0 Reserved (Note)
Bit2 -
1 Reserved (Note)
Bit1 -
1 Reserved (Note)
Bit0 -
0 Reserved (Note)
Note: Don’t write into this register, writing into this
register can cause malfunction
0600A—08/04/03
5
5 Page 
ICS932S202
Power Management Features:
PD# CPUCLK IOAPIC 3V66
0 LOW LOW LOW
PCI
PCI_F
REF.
48MHz
Osc
LOW LOW LOW OFF
VCOs
OFF
1 ON ON ON ON ON ON ON ON
Note:
1. LOW means outputs held static LOW as per latency requirement next page.
2. On means active.
3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs.
Power Management Requirements:
Signal
PD#
Signal State
1 (normal operation)
0 (power down)
Latency
No. of rising edges
of PCICLK
3mS
2max.
Note:
1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes
low/high to the first valid clock comes out of the device.
2. Power up latency is when PWR_DWN# goes inactive (high to when the first valid clocks are dirven from the device.
0600A—08/04/03
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ICS932S202.PDF ] | |
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