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PDF ICS853S014I Data sheet ( Hoja de datos )
| Número de pieza | ICS853S014I | |
| Descripción | LVPECL/ECL Fanout Buffer | |
| Fabricantes | IDT | |
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Low Skew, 1-to-5, Differential-to-2.5V, 3.3V
LVPECL/ECL Fanout Buffer
ICS853S014I
DATA SHEET
General Description
The ICS853S014I is a low skew, high performance 1-to-5, 2.5V/3.3V
Differential-to-LVPECL/ECL Fanout Buffer. The ICS853S014I has
two selectable clock inputs.
Guaranteed output and part-to-part skew characteristics make the
ICS853S014I ideal for those applications demanding well defined
performance and repeatability.
Features
• Five differential LVPECL/ECL outputs
• Two selectable differential LVPECL clock inputs
• PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
• Maximum output frequency: 2GHz
• Output skew: 55ps (maximum)
• Part-to-part skew: 100ps (maximum)
• Propagation delay: 500ps (maximum)
• Additive phase jitter, RMS: 0.10ps (maximum)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -2.375V
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
Block Diagram
nEN Pulldown
PCLK0 Pulldown
nPCLK0 Pullup/Pulldown
PCLK1 Pulldown
nPCLK1 Pullup/Pulldown
0
1
CLK_SEL Pulldown
VBB
D
Q
CLK
Pin Assignment
Q0 1
nQ0 2
20 VCC
19 nEN
Q1 3
18 VCC
Q0 nQ1 4 17 nPCLK1
Q2 5 16 PCLK1
nQ0
nQ2 6
15 VBB
Q1 Q3 7 14 nPCLK0
nQ3 8 13 PCLK0
nQ1 Q4 9 12 CLK_SEL
Q2 nQ4 10 11 VEE
nQ2 ICS853S014I
Q3 20-Lead TSSOP
nQ3 6.5mm x 4.4mm x 0.925mm package body
G Package
Q4
Top View
nQ4
ICS853S014AGI REVISION D MAY 23, 2013
1
©2013 Integrated Device Technology, Inc.
1 page  
ICS853S014I Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Table 4B. DC Characteristics, VCC = 3.3V; VEE = 0V, TA = -40°C to 85°C
-40°C
Symbol Parameter
Min Typ Max Min
VOH Output High Voltage; NOTE 1
2.175 2.275 2.50 2.225
VOL Output Low Voltage; NOTE 1
1.405 1.545 1.68 1.425
VIH Input High Voltage (CLK_SEL, nEN) 2.075
2.36 2.075
VIL
Input Low Voltage (CLK_SEL, nEN)
1.43
1.765 1.43
VBB
Output Voltage Reference;
NOTE 2
1.72
1.98 1.72
VCMR
Input High Voltage Common Mode
Range; NOTE 3
1.2
3.3 1.2
VPP
Peak-to-Peak Input Voltage;
NOTE 4
150 800 1200 150
IIH
Input
PCLK0, PCLK1
High Current nPCLK0, nPCLK1
150
IIL
Input
Low Current
PCLK0, PCLK1
nPCLK0, nPCLK1
-10
-150
-10
-150
25°C
Typ
2.295
1.52
800
Max
2.495
1.615
2.36
1.765
1.98
3.3
1200
150
NOTE: Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50 to VCC – 2V.
NOTE 2: Single-ended input operation is limited. VCC 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH for the differential inputs.
NOTE 4: The VCMR and VPP levels should be such that input low voltage never goes below VEE.
Min
2.22
1.44
2.075
1.43
1.72
1.2
150
-10
-150
85°C
Typ
2.295
1.535
800
Max
2.485
1.63
2.36
1.765
1.98
3.3
1200
150
Units
V
V
V
V
V
V
mV
µA
µA
µA
Table 4C. LVPECL DC Characteristics, VCC = 2.5V; VEE = 0V, TA = -40°C to 85°C
-40°C
25°C
Symbol Parameter
Min Typ Max Min Typ
VOH
VOL
VIH
VIL
VCMR
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage (CLK_SEL, nEN)
Input Low Voltage (CLK_SEL, nEN)
Input High Voltage Common Mode
Range; NOTE 2
1.375
0.605
1.275
0.63
1.475
0.745
1.70
0.88
1.56
0.965
1.2 2.5
1.425
0.625
1.275
0.63
1.2
1.495
0.72
VPP
Peak-to-Peak Input Voltage;
NOTE 3
150 800 1200 150 800
IIH
Input
High Current
PCLK0, PCLK1
nPCLK0, nPCLK1
150
IIL
Input
Low Current
PCLK0, PCLK1
-10
nPCLK0, nPCLK1 -150
-10
-150
Max
1.69
0.86
1.56
0.965
2.5
1200
150
NOTE: Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50 to VCC – 2V.
NOTE 2: Common mode voltage is defined as VIH for the differential inputs.
NOTE 3: The VCMR and VPP levels should be such that input low voltage never goes below VEE.
Min
1.42
0.64
1.275
0.63
1.2
150
-10
-150
85°C
Typ
1.495
0.735
800
Max
1.685
0.85
1.56
0.965
2.5
1200
150
Units
V
V
V
V
V
mV
µA
µA
µA
ICS853S014AGI REVISION D MAY 23, 2013
5
©2013 Integrated Device Technology, Inc.
5 Page 
ICS853S014I Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
LVPECL Clock Input Interface
The PCLK/nPCLK accepts LVPECL, LVDS, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 3A to 3F show interface examples
for the PCLK/nPCLK input driven by the most common driver types.
The input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm the
driver termination requirements.
3.3V
CML
3.3V
3.3V
PCLK
nPCLK
LVPECL
Input
Figure 3A. PCLK/nPCLK Input Driven by an
Open Collector CML Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
R3
125Ω
R4
125Ω
3.3V
PCLK
nPCLK
LVPECL
R1 R2
84Ω 84Ω
Input
3.3V
Zo = 50Ω
CML Built-In Pullup
Zo = 50Ω
R1
100Ω
3.3V
PCLK
nPCLK
LVPECL
Input
Figure 3B. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
3.3V
3.3V LVPECL
Zo = 50Ω
Zo = 50Ω
R5 R6
100Ω - 200Ω 100Ω - 200Ω
3.3V
C1
PCLK
C2 VBB
nPCLK
LVPECL
R1 R2
50Ω 50Ω
Input
Figure 3C. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver
Figure 3D. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver with AC Couple
2.5V
SSTL
Zo = 60Ω
Zo = 60Ω
2.5V
R3 R4
120 120
3.3V
PCLK
R1 R2
120 120
nPCLK
LVPECL
Input
3.3V
Zo = 50Ω
LVDS
Zo = 50Ω
R5
100Ω
3.3V
C1
C2
R1 R2
1k 1k
PCLK
VBB
nPCLK
LVPECL
Input
C3
0.1µF
Figure 3E. PCLK/nPCLK Input Driven by an SSTL Driver
Figure 3F. PCLK/nPCLK Input Driven by a
3.3V LVDS Driver
ICS853S014AGI REVISION D MAY 23, 2013
11
©2013 Integrated Device Technology, Inc.
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ICS853S014I.PDF ] | |
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