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PDF ICS853S006I Data sheet ( Hoja de datos )
| Número de pieza | ICS853S006I | |
| Descripción | LVPECL/ECL Fanout Buffer | |
| Fabricantes | IDT | |
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Low Skew, 1-to-6, Differential-to-
2.5V, 3.3V LVPECL/ECL Fanout Buffer
ICS853S006I
DATA SHEET
General Description
The ICS853S006I is a low skew, high performance 1-to-6
Differential-to-2.5V/3.3V LVPECL/ECL Fanout Buffer. The
ICS853S006I is characterized to operate from either a 2.5V or a
3.3V power supply. Guaranteed output and part-to-part skew
characteristics make the ICS853S006I ideal for those clock
distribution applications demanding well defined performance and
repeatability.
Features
• Six differential 2.5V, 3.3V LVPECL/ECL outputs
• One differential PCLK, nPCLK input pair
• PCLK, nPCLK pair can accept the following
differential input levels: LVPECL, LVDS, CML
• Maximum output frequency: 2GHz
• Output skew: 50ps (max)
• Part-to-part skew: 230ps (max)
• Propagation delay: 550ps (max)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.465V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -2.375V to -3.465V
• -40°C to 85°C ambient operating temperature
• Available lead-free (RoHS 6) package
Block Diagram
PCLK Pulldown
nPCLK Pullup/Pulldown
VBB
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Pin Assignment
VCC
nQ0
Q0
nQ1
Q1
nQ2
Q2
VCC
PCLK
nPCLK
1
2
3
4
5
6
7
8
9
10
20 VCC
19 Q5
18 nQ5
17 Q4
16 nQ4
15 Q3
14 nQ3
13 VCC
12 VEE
11 VBB
ICS853S006I
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm package body
G Package
Top View
ICS853S006AGI REVISION A NOVEMBER 15, 2011
1
©2011 Integrated Device Technology, Inc.
1 page  
ICS853S006I Data Sheet
LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Table 4B. LVPECL DC Characteristics, VCC = 3.3V; VEE = 0V, TA = -40°C to 85°C
-40°C
25°C
Symbol Parameter
Min Typ Max Min Typ
VOH
VOL
VSWING
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage
Swing
2.18
1.405
625
2.37
1.56
800
2.41 2.21 2.35
1.68 1.425 1.55
870 690 800
VIH Input High Voltage (Single-ended) 2.075
VIL Input Low Voltage (Single-ended) 1.43
VBB
Output Voltage Reference;
NOTE 2
1.86
2.36
1.765
2.075
1.43
1.98 1.86
VPP
VCMR
Peak-to-Peak Input Voltage
Input High Voltage Common
Mode Range; NOTE 3, 4
150 800 1200 150 800
1.2
VCC
1.2
IIH
Input
High Current
PCLK, nPCLK
150
IIL
Input
Low Current
PCLK
nPCLK
-10
-150
-10
-150
Max
2.42
1.65
870
2.36
1.765
1.98
1200
VCC
150
NOTE: Input and output parameters vary 1:1 with VCC.
NOTE 1: Outputs terminated with 50Ω to VCCO – 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V
Min
2.24
1.44
730
2.075
1.43
1.86
150
1.2
-10
-150
85°C
Typ
2.34
1.55
800
800
Max
2.41
1.65
852
2.36
1.765
1.98
1200
VCC
150
Units
V
V
mV
V
V
V
mV
V
µA
µA
µA
Table 4C. LVPECL DC Characteristics, VCC = 2.5V; VEE = 0V, TA = -40°C to 85°C
-40°C
25°C
Symbol Parameter
Min Typ Max Min Typ
VOH
VOL
VSWING
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage
Swing
1.38
0.605
625
1.57
0.76
800
1.61 1.41 1.55
0.88 0.625 0.75
870 690 800
VIH
VIL
VPP
VCMR
Input High Voltage (Single-ended) 1.275
1.56 1.275
Input Low Voltage (Single-ended)
0.63
0.965 0.63
Peak-to-Peak Input Voltage
150 800 1200 150 800
Input High Voltage Common
Mode Range; NOTE 2, 3
1.2
VCC
1.2
IIH
Input
High Current
PCLK, nPCLK
150
IIL
Input
PCLK
Low Current nPCLK
-10
-150
-10
-150
Max
1.62
0.85
870
1.56
0.965
1200
VCC
150
Min
1.44
0.64
730
1.275
0.63
150
1.2
-10
-150
NOTE: Input and output parameters vary 1:1 with VCC.
NOTE 1: Outputs terminated with 50Ω to VCCO – 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
85°C
Typ
1.54
0.75
800
800
Max
1.61
0.85
852
1.56
0.965
1200
VCC
150
Units
V
V
mV
V
V
mV
V
µA
µA
µA
ICS853S006AGI REVISION A NOVEMBER 15, 2011
5
©2011 Integrated Device Technology, Inc.
5 Page 
ICS853S006I Data Sheet
LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, LVDS, CML and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 3A to 3E show interface examples
for the PCLK/nPCLK input driven by the most common driver types.
The input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm the
driver termination requirements.
3.3V
CML
Zo = 50Ω
Zo = 50Ω
3.3V
R1 R2
50Ω 50Ω
3.3V
PCLK
nPCLK
LVPECL
Input
Figure 3A. PCLK/nPCLK Input
Driven by a CML Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
R3
125Ω
R4
125Ω
3.3V
PCLK
nPCLK
LVPECL
R1 R2
84Ω 84Ω
Input
Figure 3C. PCLK/nPCLK Input
Driven by a 3.3V LVPECL Driver
3.3V
Zo = 50Ω
LVDS
Zo = 50Ω
R5
100Ω
3.3V
C1
C2
R1 R2
1k 1k
PCLK
VBB
nPCLK
LVPECL
Input
C3
0.1µF
Figure 3E. PCLK/nPCLK Input Driven by
a 3.3V LVDS Driver
3.3V
CML Built-In Pullup
Zo = 50Ω
Zo = 50Ω
3.3V
R1
100Ω
PCLK
nPCLK
LVPECL
Input
Figure 3B. PCLK/nPCLK Input
Driven by a Built-In Pullup CML Driver
3.3V
3.3V LVPECL
Zo = 50Ω
Zo = 50Ω
R5 R6
100Ω - 200Ω 100Ω - 200Ω
3.3V
C1
PCLK
C2 VBB
nPCLK
LVPECL
R1 R2
50Ω 50Ω
Input
Figure 3D. PCLK/nPCLK Input Driven by
a 3.3V LVPECL Driver with AC Couple
ICS853S006AGI REVISION A NOVEMBER 15, 2011
11
©2011 Integrated Device Technology, Inc.
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet ICS853S006I.PDF ] | |
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