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PDF BM92A30MWV Data sheet ( Hoja de datos )

Número de pieza BM92A30MWV
Descripción USB Type-C Power Delivery Controller
Fabricantes ROHM Semiconductor 
Logotipo ROHM Semiconductor Logotipo



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Datasheet
USB Type-C Power Delivery Controller
BM92A30MWV
General Description
BM92A30 is a full function USB Type-C Power Delivery
(PD) controller that supports USB Power Delivery using
base-band communication. It is compatible with USB
Type-C Specification and USB Power Delivery
specification.
BM92A30 includes support for the PD policy engine and
communicates with an Embedded Controller or the SoC
via host interface. It supports SOP, SOP’ and SOP’’
signaling, allowing it to communicate with cable marker
ICs, support alternate modes.
Key Specifications
VBUS Voltage Range:
4.75V to 20V
Power Sink Voltage Range:
4.75V to 20V
Power Source Voltage Range:
4.75V to 5.5V
Power Consumption at Sleep Power: 0.4mW(Typ)
Operating Temperature Range: -30°C to +105°C
Package
UQFN40V5050A
W (Typ) x D (Typ) x H (Max)
5.00mm x 5.00mm x 1.00mm
Features
USB Type-C Specification compatible
USB PD Specification compatible (BMC-PHY)
Two channel power path control using N-channel
MOSFET drivers with back flow prevention
Type-C cable orientation detection
Built-in VCONN Switch and VCONN controller
Direct VBUS powered operation
Supports DFP/UFP/DRP mode
Supports Dead Battery operation
Supports Display Port control.
SMBus Interface for Host Communication
EC-less Operation (Auto mode)
Applications
Consumer Applications
Laptop PCs, Tablet PCs
Typical Application Circuit
VBUS
GND
GND
GND
HSSW
GND
GND
GND
VDDIO
VCONN
CC1
CC2
USB Type-C
Receptacle
To direct USB-PHY
D+
D-
RX1+, RX1-,
RX2+, RX2-
To direct USB-3.x PHY
TX1+, TX1-,
TX2+,TX2-
GND
VCONN_IN
CC1
CC2
XCLPOFF1
XCLPOFF2
BM92A30MWV
UQFN40V5050A
VDDIO
SMDATA
SMCLK
GPIO0HPD_OUT)
GPIO1ALERT#)
GPO2(BST_EN)
GPO3(HSSWEN)
GPIO7(MSEL1
GPIO6(MSEL0
GPIO5(ORIENT
GPIO4
VDDIO
VCCIN
DBGMODDT
DBGRSTCK
IDSEL/ATST1
VSTR/ATST2
XRST
GND
VCCIN
GND
Figure A. Typical Application Circuit
GND
GND
GND
Charger Power
Power Supply
For Prov (5V)
VSVR 3.3V
(3.1V5.5V)
External Power
VDDIO
(1.7V5.5V)
EC-I/F /
To DP_ctrl
SS/DP-MUX Control
VCCIN
EC-I/F
GND
Product structure : Silicon monolithic integrated circuit
.www.rohm.com
© 2016 ROHM Co., Ltd. All rights reserved.
TSZ22111 14 001
This product has no designed protection against radioactive rays
1/31
TSZ02201-0232AA000460-1-2
21.Sep.2016 Rev.001

1 page




BM92A30MWV pdf
BM92A30MWV
2. Pin Description
PKG
PIN#
Pin Name
1 GND
2 VSTR/ATST2
3 IDSEL/ATST1
4 XRST
5 VCCIN
6 VSVR
7 DSCHG
8 GND
9 VB
10 GPIO4
11 GPIO5(ORIENT)
12 GPIO6(MSEL0)
13 GPIO7(MSEL1)
14 DBGRSTCK
15 DBGMODDT
16
GPIO0
(HPD_OUT)
17
GPIO1
(ALERT#)
18 VDDIO
19 SMDATA
20 SMCLK
21 S2_DRV_G1
22 S2_DRV_SRC
23 S2_DRV_G2
24 S1_DRV_G1
25 S1_DRV_SRC
26 S1_DRV_G2
(Note 1) N-ch Open Drain
Table 2-1 Pin Description
BLOCK
I/O
Type
Digital
I/O Level
Description
GND
I GND
Ground
TEST/Debug IO Analog
Analog TEST/ Debug Pin2
SMBus ID (device address)
TEST/Debug I Analog VCCIN selection “H”:1Ah, “L”:18h
/Debug Pin1
Interface
I Digital VCCIN Digital block Reset
Internal Power supply
USB-PD
O Analog
(For internal use, need to
connect capacitor to GND
POWER
I Power
5V SVR INPUT and
SPDSRC_FET_SRC voltage
Interface
IO Analog
Discharge NMOS Drain
GND
I GND
Ground
POWER
I Power
Power Source from VBUS
Interface
I Digital
Mode fixation (Fix: L)
Interface
O*1 Digital
ORIENT signal
Interface
O*1 Digital
MSEL0 signal
Interface
O*1 Digital
MSEL1 signal
TEST
IO Digital VDDIO Test for logic
TEST
IO Digital VDDIO Test for logic
Interface
O Digital VDDIO Hot Plug Detect signal output
Interface
POWER
Interface
Interface
FET Gate
Control
FET Gate
Control
FET Gate
Control
FET Gate
Control
FET Gate
Control
FET Gate
Control
O *1
I
IO
I
O
Digital
Power
Digital
Digital
VDDIO
VDDIO
VDDIO
Analog
I Analog
O Analog
O Analog
I Analog
O Analog
Alert signal
Interface Voltage
SMBus Data
SMBus Clock
Power Path FET Gate Control
SPDSNK_G1
Power Path FET BG/SRC
Voltage
SPDSNK_SRC
Power Path FET Gate Control
SPDSNK_G2
Power Path FET Gate Control
SPDSRC_G1
Power Path FET BG/SRC
Voltage
SPDSRC_SRC
Power Path FET Gate Control
SPDSRC_G2
www.rohm.com
© 2016 ROHM Co., Ltd. All rights reserved.
TSZ22111 15 001
5/31
TSZ02201-0232AA000460-1-2
21.Sep.2016 Rev.001

5 Page





BM92A30MWV arduino
BM92A30MWV
4.7. Power Supply Management
4.7.1. Outline
This LSI has a power selector. It select the lowest power supply voltage from VSVR, VEX, or VB for low power consumption.
Internal Power Supply (VCCIN) gives priority in order of VSVR, VEX, and VB. VCCIN supplied from the power selector is
used to LSI main power source. LDOs (for internal only) are supplied from VCCIN, and output each internal supply voltage.
Each power supply input have UVLO and OVLO. And POR (power on reset) signal is generated from detection of
LDO28OK, LDO15DOK, LDO15AOK, and VCCIN.
UVLO
/OVLO
signal
UVLO/OVLO
Detection
Internal
Power
Supply
LDO28OK
POR
signal
Internal
Power
Supply
VDDIO
detection
signal
POR
LDO15DOK
LDO15AOK
DET
LDO
LDO
LDO
VSVR
VEX
VB
VCCIN
LDO28CAP
LDO15DCAP
LDO15ACAP
VDDIO
VBUS 0V
VEX
0V
VSVR 0V
5 to 20V
5 to 20V
5V
VCCIN 0V
VBUS
VEX
VSVR
Figure 4-1 Power Supply Management Block Diagram and Timing Chart
www.rohm.com
© 2016 ROHM Co., Ltd. All rights reserved.
TSZ22111 15 001
11/31
TSZ02201-0232AA000460-1-2
21.Sep.2016 Rev.001

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