PDF AD9951 Data sheet ( Hoja de datos )

Número de pieza	AD9951
Descripción	CMOS Direct Digital Synthesize
Fabricantes	Analog Devices
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No Preview Available ! Data Sheet 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesize AD9951 FEATURES Phase-locked loop (PLL) REFCLK multiplier (4× to 20×) 400 MSPS internal clock speed Integrated 14-bit digital-to-analog converter (DAC) 32-bit tuning word Internal oscillator; can be driven by a single crystal Phase modulation capability Multichip synchronization Phase noise ≤ −120 dBc/Hz at 1 kHz offset (DAC output) Excellent dynamic performance >80 dB SFDR at 160 MHz (±100 kHz offset) AOUT Serial I/O control 1.8 V power supply Software and hardware controlled power down APPLICATIONS Agile local oscillator (LO) frequency synthesis Programmable clock generators Test and measurement equipment Acousto-optic device drivers 48-lead TQFP/EP package Support for 5 V input levels on most digital inputs FUNCTIONAL BLOCK DIAGRAM DDS CORE PHASE ACCUMULATOR Z–1 32 PHASE OFFSET 19 COS(X) AD9951 14 DAC 14 SYSTEM CLOCK Z–1 DAC_RSET IOUT IOUT 32 14 I/O UPDATE SYNC_CLK REFCLK REFCLK 0 M U X SYNC OSCILLATOR/BUFFER ENABLE 4× TO 20× CLOCK MULTIPLIER TIMING AND CONTROL LOGIC ÷ 4 CONTROL REGISTERS M U X SYSTEM CLOCK SYNC_IN OSK PWRDWNCTL CRYSTAL OUT I/O PORT Figure 1. RESET Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2003–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page Data Sheet GENERAL DESCRIPTION The AD9951 is a direct digital synthesizer (DDS) featuring a 14-bit DAC operating up to 400 MSPS. The AD9951 uses advanced DDS technology, coupled with an internal high speed, high performance DAC to form a digitally programmable, complete high frequency synthesizer capable of generating a frequency-agile analog output sinusoidal waveform at up to 200 MHz. The AD9951 is designed to provide fast frequency AD9951 hopping and fine tuning resolution (32-bit frequency tuning word). The frequency tuning and control words are loaded into the AD9951 via a serial I/O port. The AD9951 is specified to operate over the extended industrial temperature range of −40°C to +105°C. Rev. B \| Page 3 of 28 5 Page Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS REF 0dBm PEAK 0 LOG 1R 10dB/ –10 –20 –30 ATTEN 10dB MKR1 98.0MHz –70.68dB –40 MARKER 100.000000MHz –50 –70.68dB –60 W1 S2 S3 FC –70 AA –80 1 –90 –100 CENTER 100MHz #RES BW 3kHz VBW 3kHz SPAN 200MHz SWEEP 55.56 s (401 PTS) Figure 4. FOUT = 1 MHz FCLK = 400 MSPS, WBSFDR REF 0dBm PEAK 0 LOG 10dB/ –10 1R –20 –30 ATTEN 10dB MKR1 80.0MHz –69.12dB –40 MARKER 80.000000MHz –50 –69.12dB –60 W1 S2 S3 FC –70 AA –80 1 –90 –100 CENTER 100MHz #RES BW 3kHz VBW 3kHz SPAN 200MHz SWEEP 55.56 s (401 PTS) Figure 5. FOUT = 10 MHz, FCLK = 400 MSPS, WBSFDR REF 0dBm PEAK 0 LOG 10dB/ –10 –20 –30 ATTEN 10dB 1R MKR1 0Hz –68.44dB –40 MARKER 40.000000MHz –50 –68.44dB –60 W1 S2 S3 FC –70 AA –80 1 –90 –100 CENTER 100MHz #RES BW 3kHz VBW 3kHz SPAN 200MHz SWEEP 55.56 s (401 PTS) Figure 6. FOUT = 40 MHz, FCLK = 400 MSPS, WBSFDR AD9951 REF 0dBm PEAK 0 LOG 10dB/ –10 –20 –30 ATTEN 10dB 1R MKR1 80.0MHz –61.55dB –40 MARKER 80.000000MHz –50 –61.55dB –60 W1 S2 S3 FC –70 AA –80 1 –90 –100 CENTER 100MHz #RES BW 3kHz VBW 3kHz SPAN 200MHz SWEEP 55.56 s (401 PTS) Figure 7. FOUT = 80 MHz FCLK = 400 MSPS, WBSFDR REF 0dBm PEAK 0 LOG 10dB/ –10 –20 –30 ATTEN 10dB MKR1 40.0MHz –56.2dB 1R –40 –50 –60 W1 S2 S3 FC –70 AA –80 MARKER 40.000000MHz –56.2dB 1 –90 –100 CENTER 100MHz #RES BW 3kHz VBW 3kHz SPAN 200MHz SWEEP 55.56 s (401 PTS) Figure 8 FOUT = 120 MHz, FCLK = 400 MSPS, WBSFDR REF 0dBm PEAK 0 LOG 10dB/ –10 –20 –30 ATTEN 10dB MKR1 0Hz –53.17dB 1R –40 –50 –60 W1 S2 S3 FC –70 AA –80 MARKER 80.000000MHz –53.17dB 1 –90 –100 CENTER 100MHz #RES BW 3kHz VBW 3kHz SPAN 200MHz SWEEP 55.56 s (401 PTS) Figure 9. FOUT = 160 MHz, FCLK = 400 MSPS, WBSFDR Rev. B \| Page 9 of 28 11 Page

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