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PDF KSZ8462HL Data sheet ( Hoja de datos )
| Número de pieza | KSZ8462HL | |
| Descripción | IEEE 1588 Precision Time Protocol-Enabled Two-Port 10/100Mb/s Ethernet Switch | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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KSZ8462HL/KSZ8462FHL
IEEE 1588 Precision Time Protocol-Enabled
Two-Port 10/100Mb/s Ethernet Switch
with 8 or 16 Bit Host Interface
Revision 1.0
General Description
The KSZ8462 ETHERSYNCH™ product line consists of
IEEE 1588v2-enabled Ethernet switches, providing
integrated communications and synchronization for a
range of industrial Ethernet applications.
The KSZ8462 ETHERSYNCH product enables distributed,
daisy−chained topologies preferred for Industrial Ethernet
networks. Conventional centralized (i.e., star−wired)
topologies are also supported for dual−homed, fault
tolerant arrangements.
A flexible 8- or 16−bit general bus interface is provided for
interfacing to an external host processor.
The KSZ8462 devices incorporate the IEEE 1588v2
protocol. Sub-microsecond synchronization is available via
the use of hardware based time stamping and transparent
clocks making it the ideal solution for time synchronized
Layer 2 communication in critical industrial applications.
Extensive general purpose I/O (GPIO) capabilities are
available to use with the IEEE 1588v2 PTP to efficiently
and accurately interface to locally-connected devices.
Complementing the industry’s most-integrated IEEE
1588v2 device is a precision timing protocol (PTP) v2
software stack that has been pre−qualified with the
KSZ84xx product family. The PTP stack has been
optimized around the KSZ84xx chip architecture, and is
available in source code format along with Micrel’s chip
driver.
The wire−speed, store−and−forward switching fabric
provides a full complement of quality-of-service (QoS) and
congestion control features optimized for real−time
Ethernet.
ETHERSYNCH™
The KSZ8462 product is built upon Micrel’s
industry−leading Ethernet technology, with features
designed to offload host processing and streamline your
overall design:
• Wire−speed Ethernet switching fabric with extensive
filtering
• Two integrated 10/100BASE-TX PHY transceivers,
featuring the industry’s lowest power consumption
• Full−featured QoS support
• Flexible management options that support common
standard interfaces
A robust assortment of power-management features
including energy-efficient Ethernet (EEE) have been
designed in to satisfy energy-efficient environments.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
KSZ8462 Top Level Architecture
ETHERSYNCH and LinkMD are trademarks of Micrel, Inc.
Magic Packet is a trademark of Advanced Micro Devices, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
June 11, 2014
Revision 1.0
1 page  
Micrel, Inc.
KSZ8462HL/KSZ8462FHL
Ordering Information
Part Number
KSZ8462HLI
KSZ8462FHLI
KSZ8462HLI-EVAL
Temperature Range
Package
Lead Finish Description
−40°C to +85°C
64−Pin LQFP
Pb−Free
Industrial Temperature Device with Generic Host
Interface
−40°C to +85°C
64−Pin LQFP
Pb−Free
Industrial Temperature Device with Generic Host
Interface and Fiber (100BASE-FX) support
Evaluation Board with KSZ8462HLI. Also supports the KSZ8462FHLI.
Revision History
Revision
1.0
Date
6/11/14
Summary of Changes
Initial release of KSZ8462HL/FHL product datasheet.
June 11, 2014
5
Revision 1.0
5 Page 
Micrel, Inc.
KSZ8462HL/KSZ8462FHL
TXQ Rate Control Registers ............................................................................................................................................... 180
Port 1 TXQ Rate Control Register 1 (0x0C8 – 0x0C9): P1TXQRCR1............................................................................ 180
Port 1 TXQ Rate Control Register 2 (0x0CA – 0x0CB): P1TXQRCR2 ........................................................................... 180
Port 2 TXQ Rate Control Register 1 (0x0CC – 0x0CD): P2TXQRCR1........................................................................... 181
Port 2 TXQ Rate Control Register 2 (0x0CE – 0x0CF): P2TXQRCR2 ........................................................................... 181
Port 3 TXQ Rate Control Register 1 (0x0D0 – 0x0D1): P3TXQRCR1............................................................................ 182
Port 3 TXQ Rate Control Register 2 (0x0D2 – 0x0D3): P3TXQRCR2............................................................................ 182
0x0D4 – 0x0D5: Reserved .............................................................................................................................................. 182
Input and Output Multiplex Selection Registers .................................................................................................................. 183
Input and Output Multiplex Selection Register (0x0D6 – 0x0D7): IOMXSEL.................................................................. 183
Configuration Status and Serial Bus Mode Registers......................................................................................................... 184
Configuration Status and Serial Bus Mode Register (0x0D8 – 0x0D9): CFGR .............................................................. 184
0x0DA – 0x0DB: Reserved.............................................................................................................................................. 184
Auto-Negotiation Next Page Registers ............................................................................................................................... 185
Port 1 Auto−Negotiation Next Page Transmit Register (0x0DC – 0x0DD): P1ANPT ..................................................... 185
Port 1 Auto−Negotiation Link Partner Received Next Page Register (0x0DE – 0x0DF): P1ALPRNP ........................... 186
EEE and Link Partner Advertisement Registers ................................................................................................................. 187
Port 1 EEE and Link Partner Advertisement Register (0x0E0 – 0x0E1): P1EEEA......................................................... 187
Port 1 EEE Wake Error Count Register (0x0E2 – 0x0E3): P1EEEWEC ........................................................................ 188
Port 1 EEE Control/Status and Auto−Negotiation Expansion Register (0x0E4 – 0x0E5): P1EEECS ............................ 188
Port 1 LPI Recovery Time Counter Register (0x0E6): P1LPIRTC .................................................................................. 190
Buffer Load to LPI Control 1 Register (0x0E7): BL2LPIC1 ............................................................................................. 190
Port 2 Auto−Negotiation Next Page Transmit Register (0x0E8 – 0x0E9): P2ANPT....................................................... 190
Port 2 Auto−Negotiation Link Partner Received Next Page Register (0x0EA – 0x0EB): P2ALPRNP ........................... 191
Port 2 EEE and Link Partner Advertisement Register (0x0EC – 0x0ED): P2EEEA ....................................................... 192
Port 2 EEE Wake Error Count Register (0x0EE – 0x0EF): P2EEEWEC........................................................................ 193
Port 2 EEE Control/Status and Auto−Negotiation Expansion Register (0x0F0 – 0x0F1): P2EEECS ............................ 193
Port 2 LPI Recovery Time Counter Register (0x0F2): P2LPIRTC .................................................................................. 195
PCS EEE Control Register (0x0F3): PCSEEEC ............................................................................................................. 195
Empty TXQ to LPI Wait Time Control Register (0x0F4 – 0x0F5): ETLWTC................................................................... 195
Buffer Load to LPI Control 2 Register (0x0F6 – 0x0F7): BL2LPIC2 ............................................................................... 196
0x0F8 – 0x0FF: Reserved ............................................................................................................................................... 196
Internal I/O Register Space Mapping for Interrupts, BIU, and Global Reset (0x100 – 0x1FF)........................................... 197
0x100 – 0x107: Reserved................................................................................................................................................ 197
Chip Configuration Register (0x108 – 0x109): CCR ....................................................................................................... 197
0x10A – 0x10F: Reserved ............................................................................................................................................... 197
Host MAC Address Registers: MARL, MARM and MARH .............................................................................................. 198
Host MAC Address Register Low (0x110 – 0x111): MARL............................................................................................. 198
Host MAC Address Register Middle (0x112 – 0x113): MARM........................................................................................ 198
Host MAC Address Register High (0x114 – 0x115): MARH ........................................................................................... 198
0x116 – 0x121: Reserved................................................................................................................................................ 198
EEPROM Control Register (0x122 – 0x123): EEPCR .................................................................................................... 199
Memory BIST Info Register (0x124 – 0x125): MBIR ....................................................................................................... 199
Global Reset Register (0x126 – 0x127): GRR ................................................................................................................ 200
0x128 – 0x129: Reserved................................................................................................................................................ 200
Wake-Up Frame Control Register (0x12A – 0x12B): WFCR .......................................................................................... 201
0x12C – 0x12F: Reserved............................................................................................................................................... 201
Wake-Up Frame 0 CRC0 Register (0x130 – 0x131): WF0CRC0 ................................................................................... 201
Wake-Up Frame 0 CRC1 Register (0x132 – 0x133): WF0CRC1 ................................................................................... 202
Wake-Up Frame 0 Byte Mask 0 Register (0x134 – 0x135): WF0BM0............................................................................ 202
Wake-Up Frame 0 Byte Mask 1 Register (0x136 – 0x137): WF0BM1............................................................................ 202
Wake-Up Frame 0 Byte Mask 2 Register (0x138 – 0x139): WF0BM2............................................................................ 202
Wake-Up Frame 0 Byte Mask 3 Register (0x13A – 0x13B): WF0BM3........................................................................... 202
0x13C – 0x13F: Reserved............................................................................................................................................... 203
Wake-Up Frame 1 CRC0 Register (0x140 – 0x141): WF1CRC0 ................................................................................... 203
Wake-Up Frame 1 CRC1 Register (0x142 – 0x143): WF1CRC1 ................................................................................... 203
June 11, 2014
11
Revision 1.0
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet KSZ8462HL.PDF ] | |
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