PDF CD40103BMS Data sheet ( Hoja de datos )

Número de pieza	CD40103BMS
Descripción	CMOS 8-Stage Presettable Synchronous Down Counters
Fabricantes	Intersil Corporation
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No Preview Available ! December 1992 CD40102BMS CD40103BMS CMOS 8-Stage Presettable Synchronous Down Counters Features Description • High Voltage Type (20V Rating) • CD40102BMS: 2-Decade BCD Type • CD40103BMS: 8-Bit Binary Type • Synchronous or Asynchronous Preset • Medium Speed Operation - fCL = 3.6MHz (Typ) at 10V • Cascadable • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Pack- age Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Standardized Symmetrical Output Characteristics • 5V, 10V and 15V Parametric Ratings • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Speciﬁcations for Description of ‘B’ Series CMOS Devices” CD40102BMS and CD40103BMS consist of an 8-stage syn- chronous down counter with a single output which is active when the internal count is zero. The CD40102BMS is conﬁg- ured as two cascaded 4-bit BCD counters, and the CD40103BMS contains a single 8-bit binary counter. Each type has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All con- trol inputs and the CARRY-OUT/ZERO-DETECT output are active-low logic. In normal operation, the counter is decremented by one count on each positive transition of the CLOCK. Counting is inhibited when the CARRY-IN/COUNTER ENABLE (CI/CE) inputs is high. The CARRY-OUT/ZERO-DETECT (CO/ZD) output goes low when the count reaches zero if the CI/CE input is low, and remains low for one full clock period. When the SYNCHRONOUS PRESET-ENABLE (SPE) input is low, data at the JAM input is clocked into the counter on the next positive clock transition regardless of the state of the CI/CE input. When the ASYNCHRONOUS PRESET- ENABLE (APE) input is low, data at the JAM inputs is asyn- chronously forced into the counter regardless of the state of the SPE, CI/CE, or CLOCK inputs. JAM inputs J0-J7 repre- sent two 4-bit BCD words for the CD40102BMS and a single 8-bit binary word for the CD40103BMS. Applications • Divide-By- “N” Counters • Programmable Times • Interrupt Timers • Cycle/Program Counter When the CLEAR (CLR) input is low, the counter is asyn- chronously cleared to its maximum count (9910 for the CD40102BMS and 25510 for the CD40103BMS) regardless of the state of any other input. The precedence relationship between control inputs is indicated in the truth table. If all control inputs except CI/CE are high at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 100 or 256 clock pulses long. Pinout CD40102BMS, CD40130BMS TOP VIEW CLOCK 1 CLEAR 2 CARRY IN/ 3 COUNTER ENABLE J0 4 J1 5 J2 6 J3 7 VSS 8 16 VDD 15 SYNCHRONOUS PRESET ENABLE 14 CARRY OUT/ ZERO DETECT 13 J7 12 J6 11 J5 10 J4 9 ASYNCHRONOUS PRESET ENABLE This causes the CO/ZD output to go low to enable the clock on each succeeding clock pulse. The CD40102BMS and CD40103BMS may be cascaded using the CI/CE input and the CO/ZD output, in either a syn- chronous or ripple mode as shown in Figures 16 and 17. The CD40102MS and CD40103BMS are supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack CD40102B Only H4W †H4X *H1L †H1F H6W †CD40130B Only CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 \| Copyright © Intersil Corporation 1999 7-1294 File Number 3351 1 page Speciﬁcations CD40102BMS, CD40103BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Input Capacitance SYMBOL CONDITIONS CIN Any Input NOTES 1, 2 TEMPERATURE +25oC MIN - MAX 7.5 UNITS pF NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional Propagation Delay Time SYMBOL CONDITIONS IDD VDD = 20V, VIN = VDD or GND VNTH VDD = 10V, ISS = -10µA ∆VTN VDD = 10V, ISS = -10µA VTP ∆VTP VSS = 0V, IDD = 10µA VSS = 0V, IDD = 10µA F TPHL TPLH VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND VDD = 5V NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. NOTES 1, 4 1, 4 1, 4 TEMPERATURE +25oC +25oC +25oC MIN - -2.8 - 1, 4 +25oC 0.2 1, 4 +25oC - 1 1, 2, 3, 4 +25oC +25oC VOH > VDD/2 - 3. See Table 2 for +25oC limit. 4. Read and Record MAX 25 -0.2 ±1 2.8 ±1 VOL < VDD/2 1.35 x +25oC Limit UNITS µA V V V V V ns TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 Output Current (Sink) Output Current (Source) IDD IOL5 IOH5A ± 1.0µA ± 20% x Pre-Test Reading ± 20% x Pre-Test Reading CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS 100% 5004 1, 7, 9 100% 5004 1, 7, 9 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Sample 5005 1, 7, 9 READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A Subgroups 1, 2, 3, 9, 10, 11 7-1298 5 Page CD40102BMS, CD40103BMS CI CL CL SPE SPE J CLR APE Q CI CI Q DS Q CL CL Q R TO GATING TO GATING CLR FIGURE 11. DETAIL LOGIC DIAGRAM FOR FLIP-FLOPS, FF0 - FF7, USED IN LOGIC DIAGRAMS FOR CD40102BMS AND CD40103BMS CLK CLR CI/CE SPE APE J0 J1 J2 J3 J4 J5 J6 J7 CO/ZD CD40102BMS COUNT CD40103BMS COUNT 99 98 255 254 3 3 2 1 0 99 98 98 97 8 2 1 0 255 254 254 253 8 7 6 5 4 99 98 97 96 7 6 5 4 255 254 253 252 FIGURE 12. TIMING DIAGRAM FOR CD40102BMS AND CD40103BMS 7-1304 11 Page

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