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PDF EM68B16DVAA Data sheet ( Hoja de datos )
| Número de pieza | EM68B16DVAA | |
| Descripción | 32M x 16 Mobile DDR Synchronous DRAM | |
| Fabricantes | Etron Technology | |
| Logotipo |  |
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EtronTech
EM68B16DVAA
32M x 16 Mobile DDR Synchronous DRAM (SDRAM)
Etron Confidential
Advanced (Rev. 1.0 Mar. /2009)
Features
• Fast clock rate: 166/133 MHz
• Differential Clock CK & CK
• Bi-directional DQS
• Four internal banks, 8M x 16-bit for each bank
• Edge-aligned with read data, centered in write data
• Programmable Mode and Extended Mode Registers
- CAS Latency: 2, or 3
- Burst length: 2, 4, 8, or 16
- Burst Type: Sequential & Interleaved
- PASR (Partial Array Self Refresh)
- Auto TCSR (Temperature Compensated Self
Refresh)
- DS (Drive Strength)
• Individual byte writes mask control
• DM Write Latency = 0
• Precharge Standby Current = 300 µA
• Self Refresh Current = 700 µA
• Deep power-down Current = 10 µA max. at 85
• Auto Refresh and Self Refresh
• 8192 refresh cycles / 64ms
• No DLL (Delay Lock Loop), to reduce power; CK to
DQS is not synchronized.
• Power supplies: VDD & VDDQ = +1.8V+0.15V/-0.1V
• Interface: LVCMOS
• Ambient Temperature TA = -25 ~ 85 ,
• 60-ball 8mm x 10mm VFBGA package
- Pb free and Halogen free
Table 1. Ordering Information
Part Number
Clock
Frequency
Data Rate
IDD6 Package
EM68B16DVAA-6H 166MHz 333Mbps/pin 700 µA VFBGA
EM68B16DVAA-75H 133MHz 266Mbps/pin 700 µA VFBGA
VA: indicates VFBGA package
A: indicates Generation Code
H: indicates Pb and Halogen Free for VFBGA Package
Figure 1. Ball Assignment (Top View)
123 … 789
A VSS DQ15 VSSQ
VDDQ DQ0 VDD
B VDDQ. DQ13 DQ14
C VSSQ DQ11 DQ12
DQ1 . DQ2 VSSQ
DQ3 DQ4 VDDQ
D VDDQ DQ9 DQ10
DQ5 DQ6 VSSQ
E VSSQ UDQS DQ8
DQ7 LDQS VDDQ
F VSS UDM NC
NC LDM VDD
G CKE CK
CK
WE CAS RAS
H A9 A11 A12
CS BA0 BA1
J A6 A7 A8
A10/AP A0
A1
K VSS
A4
A5
A2 A3 VDD
Overview
The EM68B16D is 536,870,912 bits of double data
rate synchronous DRAM organized as 4 banks of
8,388,608 words by 16 bits. The synchronous
operation with Data Strobe allows extremely high
performance. EM68B16D is applied to reduce
leakage and refresh currents while achieving very
high speed. I/O transactions are possible on both
edges of the clock. The ranges of operating
frequencies, programmable burst length and
programmable latencies allow the device to be
useful for a variety of high performance memory
system applications.
Etron Technology, Inc.
No. 6, Technology Rd. V, Hsinchu Science Park, Hsinchu, Taiwan 30078, R.O.C.
TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc. reserves the right to change products or specification without notice.
1 page  
EtronTech
EM68B16DVAA
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CK. Table 3
shows the truth table for the operation commands.
Table 3. Truth Table (Note (1), (2))
Command
State CKEn-1 CKEn DM BA1 BA0 A10 A12-A11, A9-0 CS RAS CAS WE
BankActivate
Idle(3)
H X X V V Row Address L L H H
BankPrecharge
Any H X X V V L X
LL HL
PrechargeAll
Write
Write and AutoPrecharge
Read
Read and Autoprecharge
Any H X X X X H X
LL HL
Active(3) H X V V V L
LH L L
Active(3)
H
X VV V H
Column
Address
L
H
LL
Active(3) H X X V V L A0~A9 L H L H
Active(3) H X X V V H
LH LH
Mode Register Set
Extended Mode Register Set
Idle
Idle
H X XL L
H X XH L
OP code
LL
LL
LL
LL
No-Operation
Any H X X X X X X
LH HH
Device Deselect
Burst Stop
Any H X X X X X X H X X X
Active(4) H X X X X X
X
LH HL
AutoRefresh
Idle H H X X X X X
LL LH
SelfRefresh Entry
Idle H L X X X X X
LL LH
SelfRefresh Exit
Idle
(Self Refresh)
L
H XX X X
X
HX
LH
XX
HH
Power Down Mode Entry
Idle/Active(5
)
H
L XX X X
X
HX
LH
XX
HH
Power Down Mode Exit
Any
(Power Down)
L
H XX X X
X
HX
LH
XX
HH
Deep Power Down Entry
Any H L X X X X X
LH HL
Deep Power Down Exit
Any L H X X X X X H X X X
Data Write/Output Enable
Active
H X LX X X
X
XX XX
Data Mask/Output Disable
Active
H X HX X X
X
XX
Note: 1. V = Valid data, X = Don't Care, L = Low level, H = High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BA0, BA1signals.
4. Read burst stop with BST command for all burst types.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
XX
Etron Confidential
5
Rev. 1.0
Mar. 2009
5 Page 
EtronTech
EM68B16DVAA
Write Interrupted by Write
A Burst Write can be interrupted by the new Write command before completion of the previous Burst Write,
with the only restriction being that the interval that separates the commands must be at least one clock cycle.
When the previous burst is interrupted, the remaining addresses are overridden by the new addresses and
the new data will be written into the device until the programmed Burst Length is satisfied.
Write Interrupted by Read & DM
A Burst Write can be interrupted by a Read command to any bank. The DQ must be in the high impedance
state at least one clock cycle before the interrupting read data appears on the outputs to avoid data
contention. When the Read command is to be asserted, any residual data from the Burst Write sequence
must be masked by DM. The delay from the last data to the Read command (tWTR) is required to avoid data
contention inside the DRAM. Data presented on the DQ pins before the Read command is initiated will
actually be written to the memory. A Read command interrupting a write sequence can not be issued at the
next clock edge following the Write command.
Write Interrupted by Precharge & DM
A Burst Write can be interrupted by a Precharge of the same bank before completion of the previous burst. A
write recovery time (tWR) is required from the last data to the Precharge command. When the Precharge
command is asserted, any residual data from the Burst Write cycle must be masked by DM.
z Burst Stop Command
The Burst Stop command is initiated by having RAS and CAS High with CS and WE Low at the rising
edge of the clock only. The Burst Stop command has the fewest restrictions, making it the easiest method to
use when terminating a burst operation before it has been completed. When the Burst Stop command is
issued during a Burst Read cycle, both the data and DQS (Data Strobe) go to a high impedance state after a
delay which is equal to the CAS latency set in the Mode Register. The Burst Stop command, however, is not
supported during a Burst Write operation.
z DM Masking Function
The DDR SDRAM has a Data Mask function that can be used in conjunction with the data write cycle only,
not the read cycle. When the Data Mask is activated (DM High) during a write operation, the write data is
masked immediately (DM to Data Mask latency is zero). DM must be issued at the rising edge or the falling
edge of Data Strobe instead of at a clock edge.
z Auto Precharge Operation
Auto Precharge is a feature which performs the same individual bank precharge function as described above,
but without requiring an explicit command. This is accomplished by using A10 (A10 = High), to enable Auto
Precharge in conjunction with a specific READ or WRITE command. A precharge of the bank / row that is
addressed with the READ or WRITE command is automatically performed upon completion of the read or
write burst. Auto Precharge is non persistent in that it is either enabled or disabled for each individual READ
or WRITE command. Auto Precharge ensures that a precharge is initiated at the earliest valid stage within a
burst. The user must not issue another command to the same bank until the precharging time (tRP) is
completed. When the Auto Precharge command is activated, the active bank automatically begins to
precharge at the earliest possible moment during a read or write cycle after tRAS (min) is satisfied.
z Precharge Command
The Precharge command is issued when CS , RAS , and WE are Low and CAS is High at the rising edge
of the clock (CK). The Precharge command can be used to precharge any bank individually or all banks
simultaneously. The Bank Select addresses (BA0, BA1) are used to define which bank is precharged when
the command is initiated. For a write cycle, tWR (min) must be satisfied from the start of the last Burst Write
cycle until the Precharge command can be issued. After tRP from the precharge, an Active command to the
same bank can be initiated.
Etron Confidential
11
Rev. 1.0
Mar. 2009
11 Page | ||
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| PDF Descargar | [ Datasheet EM68B16DVAA.PDF ] | |
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