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PDF EM639325 Data sheet ( Hoja de datos )
| Número de pieza | EM639325 | |
| Descripción | 4M x 32 bit Synchronous DRAM | |
| Fabricantes | Etron Technology | |
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EtronTech
EM639325
4M x 32 bit Synchronous DRAM (SDRAM)
Advance (Rev. 2.1, Aug. /2015)
Features
• Fast access time from clock: 5/5.4/5.4 ns
• Fast clock rate: 200/166/143 MHz
• Fully synchronous operation
• Internal pipelined architecture
• Four internal banks (1M x 32-bit x 4bank)
• Programmable Mode
- CAS Latency: 2 or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: Sequential & Interleaved
- Burst-Read-Single-Write
• Burst stop function
• Individual byte controlled by DQM0-3
• Auto Refresh and Self Refresh
• 4096 refresh cycles/64ms
• Single 3.3V ±0.3V power supply
• Industrial Temperature: TA = -40~85°C
• Interface: LVTTL
• 86-pin 400 mil plastic TSOP II package
- Pb free and Halogen free
• 90-ball 8 x 13 x 1.2mm FBGA package
- Pb and Halogen Free
Overview
The EM639325 SDRAM is a high-speed CMOS
synchronous DRAM containing 128 Mbits. It is
internally configured as a quad 1M x 32 DRAM with
a synchronous interface (all signals are registered
on the positive edge of the clock signal, CLK). Each
of the 1M x 32 bit banks is organized as 4096 rows
by 256 columns by 32 bits. Read and write accesses
to the SDRAM are burst oriented; accesses start at a
selected location and continue for a programmed
number of locations in a programmed sequence.
Accesses begin with the registration of a BankActivate
command which is then followed by a Read or Write
command.
The EM639325 provides for programmable Read
or Write burst lengths of 1, 2, 4, 8, or full page, with
a burst termination option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence. The refresh functions, either Auto or Self
Refresh are easy to use. By having a programmable
mode register, the system can choose the most
suitable modes to maximize its performance. These
devices are well suited for applications requiring
high memory bandwidth.
Table 1. Key Specifications
EM639325
tCK3 Clock Cycle time(min.)
tAC3 Access time from CLK (max.)
tRAS Row Active time(min.)
tRC Row Cycle time(min.)
-5I/6I/7I
5/6/7
5/5.4/5.4
40/42/42
55/60/63
ns
ns
ns
ns
Table 2. Ordering Information
Part Number
Frequency
Package
EM639325TS-5IG
200MHz
EM639325TS-6IG
166MHz
EM639325TS-7IG
143MHz
EM639325BK-5IH
200MHz
EM639325BK-6IH
166MHz
EM639325BK-7IH
143MHz
TS: indicates TSOP II Package
BK: indicates 8 x 13 x 1.2mm FBGA Package
I: indicates Industrial Grade
G: indicates Pb and Halogen Free for TSOP II Package
H: indicates Pb and Halogen Free for FBGA Package
TSOP II
TSOP II
TSOP II
FBGA
FBGA
FBGA
Etron Technology, Inc.
No. 6, Technology Rd. V, Hsinchu Science Park, Hsinchu, Taiwan 30078, R.O.C.
TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc. reserves the right to change products or specification without notice.
1 page  
EtronTech
EM639325
Pin Descriptions
Table 3. Pin Details
Symbol
CLK
CKE
BA0, BA1
A0-A11
CS#
RAS#
CAS#
WE#
DQM0-
DQM3
DQ0-
DQ31
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input/
Output
Description
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on
the positive edge of CLK. CLK also increments the internal burst counter and
controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. If CKE
goes low synchronously with clock(set-up and hold time same as other inputs), the
internal clock is suspended from the next clock cycle and the state of output and
burst address is frozen as long as the CKE remains low. When all banks are in the
idle state, deactivating the clock controls the entry to the Power Down and Self
Refresh modes. CKE is synchronous except after the device enters Power Down
and Self Refresh modes, where CKE becomes asynchronous until exiting the same
mode. The input buffers, including CLK, are disabled during Power Down and Self
Refresh modes, providing low standby power.
Bank Activate: BA0 and BA1 defines to which bank the BankActivate, Read, Write,
or BankPrecharge command is being applied. The bank address BA0 and BA1 is
used latched in mode register set.
Address Inputs: A0-A11 are sampled during the BankActivate command (row
address A0-A11) and Read/Write command (column address A0-A7 with A10
defining Auto Precharge) to select one location out of the 1M available in the
respective bank. During a Precharge command, A10 is sampled to determine if all
banks are to be precharged (A10 = HIGH). The address inputs also provide the op-
code during a Mode Register Set or Special Mode Register Set command.
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS# is sampled HIGH. CS#
provides for external bank selection on systems with multiple banks. It is considered
part of the command code.
Row Address Strobe: The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive edges of
CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH,"
either the BankActivate command or the Precharge command is selected by the
WE# signal. When the WE# is asserted "HIGH," the BankActivate command is
selected and the bank designated by BA is turned on to the active state. When the
WE# is asserted "LOW," the Precharge command is selected and the bank
designated by BA is switched to the idle state after the precharge operation.
Column Address Strobe: The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges of
CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column access is
started by asserting CAS# "LOW." Then, the Read or Write command is selected by
asserting WE# "LOW" or "HIGH."
Write Enable: The WE# signal defines the operation commands in conjunction with
the RAS# and CAS# signals and is latched at the positive edges of CLK. The WE#
input is used to select the BankActivate or Precharge command and Read or Write
command.
Data Input/Output Mask: Data Input Mask: DQM0-DQM3 are byte specific. Input
data is masked when DQM is sampled HIGH during a write cycle. DQM3 masks
DQ31-DQ24, DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8, and DQM0
masks DQ7-DQ0.
Data I/O: The DQ0-31 input and output data are synchronized with the positive
edges of CLK. The I/Os are byte-maskable during Reads and Writes.
Rev. 2.1
5 Aug. /2015
5 Page 
EtronTech
EM639325
Figure 10. Read to Precharge (CAS# Latency = 2, 3)
CLK
ADDRESS
T0 T1
Bank,
Col A
COMMAND READ A NOP
CAS# latency=2
tCK2, DQ
CAS# latency=3
tCK3, DQ
T2 T3 T4 T5 T6 T7 T8
NOP
NOP
Bank(s)
Precharge
tRP
NOP
Bank
Row
NOP Activate NOP
DOUT A0 DOUT A1 DOUT A2 DOUT A3
DOUT A0 DOUT A1 DOUT A2 DOUT A3
Don’t Care
5 Read and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "H", BA = Bank, A10 = "H", A0-A7 = Column Address)
The Read and AutoPrecharge command automatically performs the precharge operation after the
read operation. Once this command is given, any subsequent command cannot occur within a time
delay of {tRP(min.) + burst length}. At full-page burst, only the read operation is performed in this
command and the auto precharge function is ignored.
6 Write command
(RAS# = "H", CAS# = "L", WE# = "L", BA = Bank, A10 = "L", A0-A7 = Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least tRCD(min.) before the Write command is
issued. During write bursts, the first valid data-in element will be registered coincident with the Write
command. Subsequent data elements will be registered on each successive positive clock edge
(refer to the following figure). The DQs remain with high-impedance at the end of the burst unless
another command is initiated. The burst length and burst sequence are determined by the mode
register, which is already programmed. A full-page burst will continue until terminated (at the end of
the page it will wrap to column 0 and continue).
Figure 11. Burst Write Operation (Burst Length = 4)
CLK
T0 T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQ
DIN A0
DIN A1
DIN A2
The first data element and the write
are registered on the same clock edge
DIN A3
Don’t Care
A write burst without the AutoPrecharge function may be interrupted by a subsequent Write,
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt
coming from Write command can occur on any clock cycle following the previous Write command
(refer to the following figure).
Rev. 2.1
11 Aug. /2015
11 Page | ||
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