|
|
PDF CD40100BMS Data sheet ( Hoja de datos )
| Número de pieza | CD40100BMS | |
| Descripción | CMOS 32-Stage Static Left/Right Shift Register | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CD40100BMS (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
|
No Preview Available !
CD40100BMS
December 1992
CMOS 32-Stage Static
Left/Right Shift Register
Features
Description
• High Voltage Type (20V Rating)
• Fully Static Operation
• Shift Left/Shift Right Capability
• Multiple Package Cascading
• Recirculate Capability
• LIFO of FIFO Capability
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Standardized, Symmetrical Output Characteristics
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Serial Shift Registers
• Time Delay Circuits
• Expandable N-Bit Data Storage Stack (LIFO Operation)
CD40100BMS is a 32-Stage shift register containing 32
D-type master-slave flip-flops.
The data present at the SHIFT RIGHT INPUT is transferred
into the first register stage synchronously with the positive
CLOCK edge, provided the LEFT/RIGHT CONTROL is at a
low level, the RECIRCULATE CONTROL is at a high level,
and the CLOCK INHIBIT is low. If the LEFT/RIGHT
CONTROL is at a high level and the RECIRCULATE
CONTROL is also high, data at the SHIFT LEFT INPUT is
transferred into the 32nd register stage synchronously with
the positive CLOCK transition, provided the CLOCK INHIBIT
is low. The state of the LEFT/RIGHT CONTROL,
RECIRCULATE CONTROL, and CLOCK INHIBIT should not
be changed when the CLOCK is high.
Data is shifted one stage left or one stage right depending on
the state of the LEFT/RIGHT CONTROL, synchronously with
the positive CLOCK edge. Data clocked into the first or 32nd
register states is available at the SHIFT LEFT or SHIFT
RIGHT OUTPUT respectively, on the next negative CLOCK
transition (see Data Transfer Table). No shifting occurs on the
positive CLOCK edge if the CLOCK INHIBIT line is at a high
level. With the RECIRCULATE CONTROL low, data in the
32nd stage is shifted into the first stage when the LEFT/
RIGHT CONTROL is low and from the first stage to the 32nd
stage when the LEFT/RIGHT CONTROL is low, and from the
first state to the 32nd stage when the LEFT/RIGHT control is
high. The CD40100BMS is supplied in these 16-lead outline
packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4T
H2R
H6W
Pinout
CD40100BMS
TOP VIEW
NC 1
CLOCK INHIBIT 2
CLOCK 3
SHIFT LEFT OUT 4
NC 5
SHIFT LEFT IN 6
NC 7
VSS 8
16 VDD
15 NC
14 NC
13 LEFT/RIGHT
CONTROL
12 SHIFT RIGHT OUT
11 SHIFT RIGHT IN
10 NC
9 RECIRCULATE
CONTROL
NC = NO CONNECTION
Functional Diagram
LEFT/RIGHT
CONTROL
SHIFT RIGHT
IN 11
13
SHIFT RIGHT
OUT
12
CLOCK
4
CLOCK INHIBIT
2
SHIFT LEFT
4
OUT
SHIFT LEFT
IN
6
9
RECIRCULATE
CONTROL
VSS = 8
VDD = 16
NC = 1, 5, 7, 10, 14, 15
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
7-1277
File Number 3349
1 page  
Specifications CD40100BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Propagation Delay Time
SYMBOL
CONDITIONS
TPHL VDD = 5V
TPLH
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
NOTES
1, 2, 3, 4
TEMPERATURE
+25oC
MIN
-
3. See Table 2 for +25oC limit.
4. Read and Record
MAX
1.35 x
+25oC
Limit
UNITS
ns
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
IDD
IOL5
IOH5A
± 1.0µA
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
ON Resistance
RONDEL10 ± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
TEST
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9 Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
FUNCTION
Static Burn-In 1
Note 1
Static Burn-In 2
Note 1
Dynamic Burn-
In Note 1
Irradiation
Note 2
OPEN
GROUND
1, 4, 5, 7, 10, 12, 2, 3, 6, 8, 9, 11, 13
14, 15
1, 4, 5, 7, 10, 12,
14, 15
8
1, 5, 7, 10, 14, 15
2, 8, 13
1, 4, 5, 7, 10, 12,
14, 15
8
VDD
16
2, 3, 6, 9, 11,
13, 16
9, 16
2, 3, 6, 9, 11,
13, 16
9V ± -0.5V
4, 12
OSCILLATOR
50kHz
25kHz
3 6, 11
7-1281
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet CD40100BMS.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CD40100BMS | CMOS 32-Stage Static Left/Right Shift Register | Intersil Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |