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PDF 74LVCH16245A Data sheet ( Hoja de datos )
| Número de pieza | 74LVCH16245A | |
| Descripción | 16-bit bus transceiver | |
| Fabricantes | NXP Semiconductors | |
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74LVC16245A; 74LVCH16245A
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
Rev. 08 — 6 November 2008
Product data sheet
1. General description
The 74LVC16245A; 74LVCH16245A are 16-bit transceivers featuring non-inverting
3-state bus compatible outputs in both send and receive directions. The device features
two output enable (nOE) inputs for easy cascading and two send/receive (nDIR) inputs for
direction control. nOE controls the outputs so that the buses are effectively isolated. This
device can be used as two 8-bit transceivers or one 16-bit transceiver.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices in mixed
3.3 V and 5 V applications.
The 74LVCH16245A bus hold on data inputs eliminates the need for external pull-up
resistors to hold unused inputs.
2. Features
I 5 V tolerant inputs/outputs for interfacing with 5 V logic
I Wide supply voltage range from 1.2 V to 3.6 V
I CMOS low power consumption
I MULTIBYTE flow-through standard pin-out architecture
I Low inductance multiple power and ground pins for minimum noise and ground
bounce
I Direct interface with TTL levels
I High-impedance when VCC = 0 V
I All data inputs have bus hold. (74LVCH16245A only)
I Complies with JEDEC standard JESD8-B / JESD36
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N CDM JESD22-C101C exceeds 1000 V
I Specified from −40 °C to +85 °C and −40 °C to +125 °C
1 page  
NXP Semiconductors
74LVC16245A; 74LVCH16245A
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
terminal 1
index area
D1 A32 A31 A30 A29 A28 A27 D4
A1 D5
B20 B19 B18
D8 A26
A2
B1
A3
B2
A4
B3
A5
B4
A6
B5
A7
B6
A8
B7
A9
74LVC16245A
74LVCH16245A
GND(1)
A25
B17
A24
B16
A23
B15
A22
B14
A21
B13
A20
B12
A19
B11
A18
A10 D6
B8 B9 B10
D7 A17
D2 A11 A12 A13 A14 A15 A16 D3
Transparent top view
001aai894
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.
Fig 6. Pin configuration SOT1025-1 (HUQFN60U)
74LVC_LVCH16245A_8
Product data sheet
Rev. 08 — 6 November 2008
© NXP B.V. 2008. All rights reserved.
5 of 19
5 Page 
NXP Semiconductors
74LVC16245A; 74LVCH16245A
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
VI
nOE input
GND
VCC
output
LOW-to-OFF
OFF-to-LOW
VOL
VOH
output
HIGH-to-OFF
OFF-to-HIGH
GND
VM
tPLZ
tPZL
tPHZ
VX
VY
VM
tPZH
VM
outputs
enabled
outputs
disabled
outputs
enabled
mna362
Fig 8.
Measurement points are given in Table 8.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
3-state enable and disable times.
Table 8. Measurement points
Supply voltage Input
VCC
1.2 V
2.7 V
VI
VCC
2.7 V
3.0 V to 3.6 V
2.7 V
VM
0.5 × VCC
1.5 V
1.5 V
Output
VM
0.5 × VCC
1.5 V
1.5 V
VX
VOL + 0.1 V
VOL + 0.3 V
VOL + 0.3 V
VY
VOH − 0.1 V
VOH − 0.3 V
VOH − 0.3 V
74LVC_LVCH16245A_8
Product data sheet
Rev. 08 — 6 November 2008
© NXP B.V. 2008. All rights reserved.
11 of 19
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet 74LVCH16245A.PDF ] | |
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