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PDF ADuC848 Data sheet ( Hoja de datos )
| Número de pieza | ADuC848 | |
| Descripción | 24-/16-Bit ADCs | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
FEATURES
High resolution Σ-Δ ADCs
2 independent 24-bit ADCs on the ADuC845
Single 24-bit ADC on the ADuC847 and
single 16-bit ADC on the ADuC848
Up to 10 ADC input channels on all parts
24-bit no missing codes
22-bit rms (19.5 bit p-p) effective resolution
Offset drift 10 nV/°C, gain drift 0.5 ppm/°C chop enabled
Memory
62-kbyte on-chip Flash/EE program memory
4-kbyte on-chip Flash/EE data memory
Flash/EE, 100-year retention, 100 kcycle endurance
3 levels of Flash/EE program memory security
In-circuit serial download (no external hardware)
High speed user download (5 sec)
2304 bytes on-chip data RAM
8051-based core
8051-compatible instruction set
High performance single-cycle core
32 kHz external crystal
On-chip programmable PLL (12.58 MHz max)
3 × 16-bit timer/counter
24 programmable I/O lines, plus 8 analog or
digital input lines
11 interrupt sources, two priority levels
Dual data pointer, extended 11-bit stack pointer
On-chip peripherals
Internal power-on reset circuit
12-bit voltage output DAC
Dual 16-bit Σ-Δ DACs
On-chip temperature sensor (ADuC845 only)
Dual excitation current sources (200 µA)
Time interval counter (wake-up/RTC timer)
UART, SPI®, and I2C® serial I/O
High speed dedicated baud rate generator (incl. 115,200)
Watchdog timer (WDT)
Power supply monitor (PSM)
MicroConverter® Multichannel
24-/16-Bit ADCs with Embedded 62 kB
Flash and Single-Cycle MCU
ADuC845/ADuC847/ADuC848
Power
Normal: 4.8 mA max @ 3.6 V (core CLK = 1.57 MHz)
Power-down: 20 µA max with wake-up timer running
Specified for 3 V and 5 V operation
Package and temperature range:
52-lead MQFP (14 mm × 14 mm), −40°C to +125°C
56-lead LFCSP (8 mm × 8 mm), −40°C to +85°C
APPLICATIONS
Multichannel sensor monitoring
Industrial/environmental instrumentation
Weigh scales, pressure sensors, temperature monitoring
Portable instrumentation, battery-powered systems
Data logging, precision system monitoring
AIN1
AIN10
AINCOM
REFIN2+
REFIN2–
REFIN–
REFIN+
RESET
DVDD
DGND
FUNCTIONAL BLOCK DIAGRAM
AVCO
ADuC845
AVDD
CURRENT
SOURCE
MUX
BUF
PGA
PRIMARY
24-BIT S-D ADC
12-BIT
DAC
BUF
AGND
TEMP
SENSOR
AUXILIARY
24-BIT S-D ADC
DUAL 16-BIT
S-D DAC
DUAL 16-BIT
PWM
MUX
IEXC1
IEXC2
DAC
PWM0
PWM1
EXTERNAL
VREF
DETECT
INTERNAL
BAND GAP
VREF
SINGLE-CYCLE 8061-BASED MCU
POR
OSC
PLL AND PRG
CLOCK DIV
WAKE-UP/
RTC TIMER
62 kBYTES FLASH/EE PROGRAM MEMORY
4 kBYTES FLASH/EE DATA MEMORY
2304 BYTES USER RAM
3 × 16 BIT TIMERS
BAUD RATE TIMER
POWER SUPPLY MON
WATCHDOG TIMER
4 × PARALLEL
PORTS
UART, SPI, AND I 2C
SERIAL I/O
XTAL1 XTAL2
Figure 1. ADuC845 Functional Block Diagram
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2004–2012 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
ADuC845/ADuC847/ADuC848
Parameter
Normal Mode Rejection 50 Hz/60 Hz2
On AIN
Analog Input Current2
Analog Input Current Drift
Average Input Current
Average Input Current Drift
Absolute AIN Voltage Limits2
Absolute AIN Voltage Limits2
EXTERNAL REFERENCE INPUTS
REFIN(+) to REFIN(–) Voltage
REFIN(+) to REFIN(–) Range2
Average Reference Input Current
Average Reference Input Current
Drift
NOXREF Trigger Voltage
Common-Mode Rejection
DC Rejection
50 Hz/60 Hz Rejection2
Normal Mode Rejection 50 Hz/60 Hz2
AUXILIARY ADC (ADuC845 Only)
Conversion Rate
No Missing Codes2
Resolution
Output Noise
Integral Nonlinearity
Offset Error3
Offset Error Drift2
Full-Scale Error4
Gain Error Drift4
Power Supply Rejection
Footnotes at end of table.
Min Typ
75
100
67
100
AGND +
0.1
AGND −
0.03
1
0.3
±5
±15
±125
±2
2.5
±1
±0.1
Max
±1
±5
AVDD −
0.1
AVDD +
0.03
AVDD
0.65
125
90
75
100
67
100
5.4 105
16.06
1365
24
24
See Table 19 and Table 21
See Table 18 and Table 20
±15
±3
±0.25
10
200
±0.5
±0.5
80
80
Unit
dB
dB
dB
dB
nA
nA
pA/°C
pA/°C
nA/V
pA/V/°C
V
V
V
V
µA/V
nA/V/°C
V
dB
dB
dB
dB
dB
dB
Hz
Hz
Bits
Bits
ppm of FSR
µV
LSB16
nV/°C
nV/°C
LSB16
ppm/°C
dB
dB
Conditions
50 Hz/60 Hz ± 1 Hz, 16.6 Hz Fadc, SF = 52H,
chop on, REJ60 on
50 Hz ± 1 Hz, 16.6 Hz Fadc, SF = 52H, chop on
50 Hz/60 Hz ± 1 Hz, 50 Hz Fadc, SF = 52H,
chop off, REJ60 on
50 Hz ± 1 Hz, 50 Hz Fadc, SF = 52H, chop off
TMAX = 85°C, buffer on
TMAX = 125°C, buffer on
TMAX = 85°C, buffer on
TMAX = 125°C, buffer on
±2.56 V range, buffer bypassed
Buffer bypassed
AIN1…AIN10 and AINCOM with buffer enabled
AIN1…AIN10 and AINCOM with buffer bypassed
REFIN refers to both REFIN and REFIN2
REFIN refers to both REFIN and REFIN2
Both ADCs enabled
NOXREF (ADCSTAT.4) bit active if VREF > 0.3 V, and
inactive if VREF > 0.65 V
AIN = 1 V, range = ±2.56 V
50 Hz/60 Hz ± 1 Hz, AIN = 1 V,
range = ±2.56 V, SF = 82
50 Hz/60 Hz ±1 Hz, AIN = 1 V, range = ±2.56 V,
SF = 52H, chop on, REJ60 on
50 Hz ± 1 Hz, AIN = 1 V, range = ±2.56 V,
SF = 52H, chop on
50 Hz/60 Hz ± 1 Hz, AIN = 1 V, range = ±2.56 V,
SF = 52H, chop off, REJ60 on
50 Hz ± 1 Hz, AIN = 1 V, range = ±2.56 V,
SF = 52H, chop off
Chop on
Chop off
≤26.7 Hz update rate, chop enabled
80.3 Hz update rate, chop disabled
Output noise varies with selected update rates.
1 LSB16
Chop on
Chop off
Chop on
Chop off
AIN = 1 V, range = ±2.56 V, chop enabled
AIN = 1 V, range = ±2.56 V, chop disabled
Rev. C | Page 5 of 108
5 Page 
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADuC845/ADuC847/ADuC848
52 51 50 49 48 47 46 45 44 43 42 41 40
P1.0/AIN1
P1.1/AIN2
P1.2/AIN3/REFIN2+
P1.3/AIN4/REFIN2–
AVDD
AGND
REFIN–
REFIN+
1
2
3
4
5
6
7
8
P1.4/AIN5 9
P1.5/AIN6 10
P1.6/AIN7/IEXC1 11
P1.7/AIN8/IEXC2 12
AINCOM/DAC 13
PIN 1
IDENTIFIER
ADuC845/ADuC847/ADuC848
TOP VIEW
(Not to Scale)
39 P2.7/PWMCLK
38 P2.6/PWM1
37 P2.5/PWM0
36 P2.4/T2EX
35 DGND
34 DVDD
33 XTAL2
32 XTAL1
31 P2.3/SS/T2
30 P2.2/MISO
29 P2.1/MOSI
28 P2.0/SCLOCK (SPI)
27 SDATA
14 15 16 17 18 19 20 21 22 23 24 25 26
P1.1/AIN2
P1.2/AIN3/REFIN2+
P1.3/AIN4/REFIN2–
AVDD
AGND
AGND
REFIN–
REFIN+
P1.4/AIN5
P1.5/AIN6
P1.6/AIN7/IEXC1
P1.7/AIN8/IEXC2
AINCOM/DAC
DAC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ADuC845/ADuC847/
ADuC848
TOP VIEW
(Not to Scale)
42 P2.7/PWMCLK
41 P2.6/PWM1
40 P2.5/PWM0
39 P2.4/T2EX
38 DGND
37 DGND
36 DVDD
35 XTAL2
34 XTAL1
33 P2.3/SS/T2
32 P2.2/MISO
31 P2.1/MOSI
30 P2.0/SCLOCK (SPI)
29 SDATA
Figure 2. 52-Lead MQFP Pin Configuration
Table 3. Pin Function Descriptions
Pin No: Pin No:
52-MQFP 56-LFCSP Mnemonic
1 56 P1.0/AIN1
Type1
I
21
P1.1/AIN2
I
32
P1.2/AIN3/REFIN2+ I
43
P1.3/AIN4/REFIN2− I
54
65
--- 6
77
88
Footnotes at end of table.
AVDD
AGND
AGND
REFIN−
REFIN+
S
S
S
I
I
NOTES
1. THE EXPOSED PADDLE MUST BE LEFT UNCONNECTED.
Figure 3. 56-Lead LFCSP Pin Configuration
Description
By power-on default, P1.0/AIN1 is configured as the AIN1 analog input.
AIN1 can be used as a pseudo differential input when used with AINCOM or as
the positive input of a fully differential pair when used with AIN2.
P1.0 has no digital output driver. It can function as a digital input for which 0
must be written to the port bit. As a digital input, this pin must be driven high
or low externally.
On power-on default, P1.1/AIN2 is configured as the AIN2 analog input.
AIN2 can be used as a pseudo differential input when used with AINCOM or as
the negative input of a fully differential pair when used with AIN1.
P1.1 has no digital output driver. It can function as a digital input for which 0
must be written to the port bit. As a digital input, this pin must be driven high
or low externally.
On power-on default, P1.2/AIN3 is configured as the AIN3 analog input.
AIN3 can be used as a pseudo differential input when used with AINCOM or as
the positive input of a fully differential pair when used with AIN4.
P1.2 has no digital output driver. It can function as a digital input for which 0
must be written to the port bit. As a digital input, this pin must be driven high
or low externally. This pin also functions as a second external differential
reference input, positive terminal.
On power-on default, P1.3/AIN4 is configured as the AIN4 analog input.
AIN4 can be used as a pseudo differential input when used with AINCOM or as
the negative input of a fully differential pair when used with AIN3.
P1.3 has no digital output driver. It can function as a digital input for which 0
must be written to the port bit. As a digital input, this pin must be driven high
or low externally. This pin also functions as a second external differential
reference input, negative terminal.
Analog Supply Voltage.
Analog Ground.
A second analog ground is provided with the LFCSP version only.
External Differential Reference Input, Negative Terminal.
External Differential Reference Input, Positive Terminal.
Rev. C | Page 11 of 108
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADuC848.PDF ] | |
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