PDF 9DBV0431 Data sheet ( Hoja de datos )

Número de pieza	9DBV0431
Descripción	4-output 1.8V PCIe Gen1-2-3 Zero-delay/Fanout Buffer
Fabricantes	IDT
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No Preview Available ! 4-output 1.8V PCIe Gen1-2-3 Zero-delay/Fanout Buffer (ZDB/FOB) 9DBV0431 DATASHEET Description The 9DBV0431 is a member of IDT's SOC-Friendly 1.8V Very-Low-Power (VLP) PCIe family. It can also be used for 50M or 125M Ethernet Applications via software frequency selection. The device has 4 output enables for clock management, and 3 selectable SMBus addresses. Recommended Application 1.8V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB) Output Features • 4 - 1-200Hz Low-Power (LP) HCSL DIF pairs w/ZO=100ohms Key Specifications • DIF cycle-to-cycle jitter <50ps • DIF output-to-output skew <50ps • DIF additive phase jitter is <100fs rms for PCIe Gen3 • DIF additive phase jitter <300fs rms for 12k-20MHz Block Diagram Features/Benefits • LP-HCSL outputs save 8 resistors; minimal board space and BOM cost • 53mW typical power consumption in PLL mode; minimal power consumption • OE# pins; support DIF power management • HCSL compatible differential input; can be driven by common clock sources • Programmable Slew rate for each output; allows tuning for various line lengths • Programmable output amplitude; allows tuning for various application environments • Pin/software selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application • Outputs blocked until PLL is locked; clean system start-up • Software selectable 50MHz or 125MHz PLL operation; useful for Ethernet applications • Configuration can be accomplished with strapping pins; SMBus interface not required for device control • 3.3V tolerant SMBus interface works with legacy controllers • Space saving 32-pin 5x5mm VFQFPN; minimal board space • Selectable SMBus addresses; multiple devices can easily share an SMBus segment vOE(3:0)# 4 CLK_IN CLK_IN# vSADR ^vHIBW_BYPM_LOBW# ^CKPWRGD_PD# SDATA_3.3 SCLK_3.3 SS- Compatible PLL CONTROL LOGIC DIF3 DIF2 DIF1 DIF0 9DBV0431 REVISION E 04/28/16 1 ©2016 Integrated Device Technology, Inc. 1 page 9DBV0431 DATASHEET Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 9DBV0431. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. PARAMETER SYMBOL CONDITIONS Power supply voltage VDDxx Applies to all VDD pins Input Voltage VIN Input High Voltage, SMBus VIHSMB SMBus clock and data pins Storage Temperature Ts Junction Temperature Tj Input ESD protection ESD prot Human Body Model 1Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied nor guaranteed. 3 Not to exceed 2.5V. MIN -0.5 -0.5 -65 2000 TYP MAX 2.5 VDD+0.5V 3.6V 150 125 UNITS V V V °C °C V NOTES 1,2 1, 3 1 1 1 1 Electrical Characteristics–Clock Input Parameters TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP Input High Voltage - DIF_IN VIHDIF Input Low Voltage - DIF_IN Input Common Mode Voltage - DIF_IN VILDIF VCOM Differential inputs (single-ended measurement) Differential inputs (single-ended measurement) Common Mode Input Voltage 600 800 VSS - 300 300 0 Input Amplitude - DIF_IN Input Slew Rate - DIF_IN VSWING Peak to Peak value (VIHDIF - VILDIF), single-ended dv/dt Measured differentially 300 0.4 Input Leakage Current IIN VIN = VDD , VIN = GND Input Duty Cycle dtin Measurement from differential wavefrom Input Jitter - Cycle to Cycle JDIFIn Differential Measurement 1 Guaranteed by design and characterization, not 100% tested in production. 2 Slew rate measured through +/-75mV window centered around differential zero -5 45 0 MAX 1150 UNITS NOTES mV 1 300 mV 1 725 1450 5 55 150 mV mV V/ns uA % ps 1 1 1,2 1 1 1 REVISION E 04/28/16 5 4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB) 5 Page 9DBV0431 DATASHEET SMBus Table: Output Enable Register 1 Byte 0 Name Control Function Type 0 Bit 7 Reserved Bit 6 DIF OE3 Output Enable RW Low/Low Bit 5 DIF OE2 Output Enable RW Low/Low Bit 4 Reserved Bit 3 DIF OE1 Output Enable RW Low/Low Bit 2 Reserved Bit 1 DIF OE0 Output Enable RW Low/Low Bit 0 Reserved 1. A low on these bits will overide the OE# pin and force the differential output Low/Low 1 Enabled Enabled Enabled Enabled Default 1 1 1 1 1 1 1 1 SMBus Table: PLL Operating Mode and Output Amplitude Control Register Byte 1 Bit 7 Bit 6 Name PLLMODERB1 PLLMODERB0 Control Function PLL Mode Readback Bit 1 PLL Mode Readback Bit 0 Type R R Bit 5 PLLMODE_SWCNTRL Enable SW control of PLL Mode RW Bit 4 PLLMODE1 PLL Mode Control Bit 1 Bit 3 PLLMODE0 PLL Mode Control Bit 0 Bit 2 Reserved Bit 1 Bit 0 AMPLITUDE 1 AMPLITUDE 0 Controls Output Amplitude 1. B1[5] must be set to a 1 for these bits to have any effect on the part. RW1 RW1 RW RW 01 See PLL Operating Mode Table Values in B1[7:6] Values in B1[4:3] set PLL Mode set PLL Mode See PLL Operating Mode Table 00 = 0.6V 10= 0.8V 01 = 0.7V 11 = 0.9V Default Latch Latch 0 0 0 1 1 0 SMBus Table: DIF Slew Rate Control Register Byte 2 Name Control Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SLEWRATESEL DIF3 SLEWRATESEL DIF2 SLEWRATESEL DIF1 SLEWRATESEL DIF0 Reserved Slew Rate Selection Slew Rate Selection Reserved Slew Rate Selection Reserved Slew Rate Selection Reserved Type RW RW RW RW 0 2 V/ns 2 V/ns 2 V/ns 2 V/ns 1 3 V/ns 3 V/ns 3 V/ns 3 V/ns Default 1 1 1 1 1 1 1 1 SMBus Table: Frequency Select Control Register Byte 3 Bit 7 Bit 6 Bit 5 Name FREQ_SEL_EN Control Function Reserved Reserved Enable SW selection of frequency Bit 4 FSEL1 Freq. Select Bit 1 Bit 3 FSEL0 Freq. Select Bit 0 Bit 2 Bit 1 Bit 0 SLEWRATESEL FB Reserved Reserved Adjust Slew Rate of FB 1. B3[5] must be set to a 1 for these bits to have any effect on the part. Type RW RW1 RW1 RW 01 SW frequency change disabled SW frequency change enabled See Frequency Select Table 2 V/ns 3 V/ns Default 1 1 0 0 0 1 1 1 Byte 4 is Reserved and reads back 'hFF REVISION E 04/28/16 11 4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB) 11 Page

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