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PDF 8V79S680 Data sheet ( Hoja de datos )
| Número de pieza | 8V79S680 | |
| Descripción | JESD204B Compliant Fanout Buffer and Divider | |
| Fabricantes | IDT | |
| Logotipo |  |
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JESD204B Compliant Fanout Buffer
and Divider
8V79S680
Datasheet
Description
The 8V79S680 is a fully integrated, clock and SYSREF signal fanout
buffer for JESD204B applications. It is designed as a high-performance
clock and converter synchronization solution for wireless base station
radio equipment boards with JESD204B subclass 0, 1 and 2
compliance. The main function of the device is the distribution and
fanout of high-frequency clocks and low-frequency system reference
signals generated by a JESB204B clock generator such as the IDT
8V19N480, extending its fanout capabilities and providing additional
phase-delay. The 8V79S680 is optimized to deliver very low phase noise
clocks and precise, phase-adjustable SYSREF synchronization signals
as required in GSM, WCDMA, LTE, LTE-A radio board implementations.
Low-skew outputs, low device-to-device skew characteristics and fast
output rise/fall times help the system design to achieve deterministic
clock and SYSREF phase relationship across devices.
The device distributes the input clock (CLK) and JESD204B SYSREF
signals (REF) to four fanout channels. In each channel, both input clock
and SYSREF signals are fanned-out to multiple clock (QCLK) and
SYSREF (QREF) outputs. Clock signals can be frequency-divided in
each channel. Configurable phase-delay circuits are available for both
clock and SYSREF signals. The propagation delays in all signal paths
are fully deterministic to support fixed phase relationships between clock
and SYSREF signals within one device. Clock divider can be bypassed
for low-latency clock paths. The device facilitates synchronization
between frequency dividers within the device and across multiple
devices, removing phase ambiguity introduced in dividers between
power and configuration cycles.
Each channel supports clock frequencies up to 3GHz. In an alternative
configuration, for instance JESD204B subclass 0 and 2, the SYSREF
(QREF) outputs can be configured as regular clock outputs adding
additional clock fanout to the device.
All outputs are very flexible in amplitude configuration, output signal
termination and allow both DC and AC coupling. Outputs can be
disabled and powered-down when not used. The SYSREF output
pre-bias feature supports prevention of power-on glitches and enables
AC-coupling of the system synchronization signals.
The device is configured through a 3-wire SPI serial interface. The
device is packaged in a lead-free (RoHS 6) 64-lead VFQFN package.
The extended temperature range supports wireless infrastructure,
telecommunication and networking end equipment requirements. The
device is a member of the high-performance clock family from IDT.
Features
▪ Supports high-speed, low phase noise converter clocks
▪ Distribution, fanout, phase-delay of clock and SYSREF signals
▪ Very low output noise floor: -158.8dBc/Hz noise floor
(245.76MHz)
▪ Supports clock frequencies up to 3GHz, including clock output
frequencies of 983.04MHz, 491.52MHz, 245.76MHz and
122.88MHz
▪ 4 output channels with a total of 16 differential outputs, organized
in:
— 8 dedicated clock outputs
— 8 outputs configurable as SYSREF outputs with individual
phase delay stages, or configurable as additional clock outputs
▪ Each channel contains:
— frequency dividers: ÷1, ÷2, ÷4, ÷6, ÷8, ÷12, ÷16
— clock phase delay circuits
▪ Clock phase delay circuits
— Clock: delay unit is the clock period; 256 steps
— SYSREF: Configurable precision phase delay circuits: 8 steps
of 131ps, 262ps, 393ps or 524ps
▪ Flexible differential outputs:
— LVDS/LVPECL configurable
— Amplitude configurable
— Power-down modes for unused outputs
— Supports DC and AC coupling
— QREF (SYSREF) output pre-bias feature to prevent glitches
when turning output on or off
▪ Supply voltage:
— 3.3V core and signal I/O
— 1.8V Digital control SPI I/O (3.3V-tolerant inputs)
▪ 64 VFQFN-P package (9mm x 9mm x 0.85mm)
▪ Ambient temperature range: -40°C to +85°C
Typical Applications
▪ JESD204B low phase noise clock and SYSREF signal distribution
▪ Supports JESD204 subclass 0, 1 and 2
▪ Clock distribution device for jitter-sensitive ADC and DAC circuits
▪ Wireless infrastructure
▪ Radar and imaging
▪ Instrumentation and medical
©2016 Integrated Device Technology, Inc.
1
August 4, 2016
1 page  
8V79S680 Datasheet
Table 1: Pin Descriptions (Continued)
Number
Name
Typea
Description
37 VDD_QREFA01 Power
38 VDD_QCLKA Power
39,
40
nQCLK_A0,
QCLK_A0
Output
Positive supply voltage (3.3V) for the QREF_A[1:0] outputs.
Positive supply voltage (3.3V) for the QCLK_A[2:0] outputs.
Differential clock output QCLK_A0. Configurable LVPECL/LVDS style and amplitude.
41,
42
43,
44
45
46
47,
48
49
50
51, 52
53
54
55
56
57
58, 59
60
61
62
63
nQCLK_A1,
QCLK_A1
nQCLK_A2,
QCLK_A2
VDD_QCLKA
VDD_QREFA2
nQREF_A2,
QREF_A2
VDD_QREFA2
VDD_REF
REF, nREF
Output
Output
Power
Power
Output
Power
Power
Input
VTR –
VDD_REF
RES_CAL
VDD_CLK
Power
Analog
Power
VTC –
nCLK, CLK
VDD_CLK
SDAT
SCLK
Input
Power
Input/
Output
Input
nCS Input
Differential clock output QCLK_A1. Configurable LVPECL/LVDS style and amplitude.
Differential clock output QCLK_A2. Configurable LVPECL/LVDS style and amplitude.
Positive supply voltage (3.3V) for the QCLK_A[2:0] outputs.
Positive supply voltage (3.3V) for the QREF_A2 output.
Differential SYSREF/clock output QREF_A2. LVDS style for SYSREF operation,
configurable LVPECL/LVDS style and amplitude for clock operation.
Positive supply voltage (3.3V) for the QREF_A2 output.
Positive supply voltage (3.3V) for the differential SYSREF input REF, nREF
SYSREF inverting and non-inverting differential input. Compatible with LVPECL and LVDS
signals. REF and nREF are internally 50terminated to the VTR pin
Internal termination for the differential clock input REF, nREF. Both REF and nREF inputs
are internally terminated 50 to this pin. See input termination information in Section
“Application Information”.
Positive supply voltage (3.3V) for the differential SYSREF input REF, nREF
Connect a 2.8 k (1%) resistor to GND for output current calibration.
Positive supply voltage (3.3V) for the differential device clock input CLK, nCLK.
Internal termination for the differential clock input CLK, nCLK. Both CLK and nCLK inputs
are internally 50terminated to the VTR pin. See input termination information in Section
“Application Information”.
Device clock inverting and non-inverting differential clock input. Compatible with LVPECL
and LVDS signals. CLK and nCLK are internally terminated to VTC through 50.
Positive supply voltage (3.3V) for the differential device clock input CLK, nCLK.
Serial Control Port SPI Mode Data Input and Output. 1.8V LVCMOS/LVTTL interface
levels. 3.3V tolerant when input.
PD
Serial Control Port SPI Mode Clock Input. 1.8V LVCMOS/LVTTL interface levels.
3.3V-tolerant when input.
PU
Serial Control Port SPI Chip Select Input. 1.8V LVCMOS/LVTTL interface levels and 3.3V
tolerant.
64
Exposed
Pad (EP)
VDD_SPI
GND
Power
Power
Positive supply voltage (3.3V) for the SPI interface.
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
a. Internal pull-up (PU) and pull-down (PD) resistors are indicated in parentheses. See Table 22 for values.
©2016 Integrated Device Technology, Inc
5
August 4, 2016
5 Page 
8V79S680 Datasheet
Table 8: Individual Clock Output (QCLK_y) Settingsa
PD STYLE EN A[1:0] Output Power
Terminationb
1XX
X
0 XX
Off 100 differential (LVDS) or no termination
00
0 01
1
10
100 differential (LVDS)
11
0
0 XX
00
1 01
1
10
11
On
50 to VT (LVPECL)
a. Applicable to clock outputs: QCLK_y and QREF_r outputs in clock mode (MUX_r = 0).
b. See Section “Application Information” on page 42 for output termination information.
c. Differential output is disabled in static low state: QCLK_y = L, nQCLK_y = H.
Table 9: Individual SYSREF Output (QREF_r) Settingsa
PD STYLE Enable A[1:0] nBIAS
Output
Power
Terminationb
1X
XX
X
Off
100 differential or no
termination
0 XX
0
00 0
0
0 01
11
100 differential (LVDS)
10 0
0
11 0
On
0 XX
00
1 01 0
1
10
11
50 to VT (LVPECL)
a. Applicable QREF_r outputs when configured as SYSREF output (MUX_r = 1).
b. See Section “Application Information” on page 42 for output termination information.
c. Differential output is disabled in static low state: QCLK_y = L, nQCLK_y = H.
State
Off
Disablec
Enable
Disable
Enable
State
Off
Disablec
Enabled
See Table 10
Enabled
Disable
Enable
Amplitude (mV)
X
X
250
500
750
1000
X
250
500
750
1000
Amplitude (mV)
X
X
250
500
750
1000
X
250
500
750
1000
©2016 Integrated Device Technology, Inc
11
August 4, 2016
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 8V79S680.PDF ] | |
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