|
|
PDF IDT8SLVP2102I Data sheet ( Hoja de datos )
| Número de pieza | IDT8SLVP2102I | |
| Descripción | LVPECL Output Fanout Buffer | |
| Fabricantes | IDT | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de IDT8SLVP2102I (archivo pdf) en la parte inferior de esta página. Total 23 Páginas | ||
|
No Preview Available !
Low Phase Noise, Dual 1-to-2, 3.3V, 2.5V
LVPECL Output Fanout Buffer
IDT8SLVP2102I
DATASHEET
General Description
The IDT8SLVP2102I is a high-performance differential LVPECL
fanout buffer. The device is designed for the fanout of high-frequency,
very low additive phase-noise clock and data signals. The
IDT8SLVP2102I is characterized to operate from a 3.3V or 2.5V
power supply. Guaranteed output-to-output and part-to-part skew
characteristics make the IDT8SLVP2102I ideal for those clock
distribution applications demanding well-defined performance and
repeatability. Two selectable differential inputs and four low skew
outputs are available. The integrated bias voltage reference enables
easy interfacing of single-ended signals to the device inputs. The
device is optimized for low power consumption and low additive
phase noise.
Features
• Two low skew, low additive jitter LVPECL output pairs
• Two selectable, differential clock input pairs
• Differential pairs can accept the following differential input
levels: LVDS, LVPECL, CML
• Maximum input clock frequency: 2GHz
• Output skew: 5ps (typical)
• Propagation delay: 225ps (maximum)
• Low additive phase jitter, RMS, fREF = 156.25MHz, VPP = 1V,
12kHz – 20MHz: 36fs (maximum)
• Full 3.3V and 2.5V supply voltage
• Maximum device current consumption (IEE): 56mA (maximum)
• Available in lead-free (RoHS 6), 16-Lead VFQFN package
• -40°C to 85°C ambient operating temperature
• Accept single-ended LVCMOS levels. See Applications section
• Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can also
accept single-ended LVCMOS levels. See Applications section
Wiring the Differential Input Levels to Accept Single-ended Levels
(Figure 1A and Figure 1B)
Block Diagram
VCC
PCLKA
nPCLKA
PCLKB
nPCLKB
VCC
VREF
Voltage
Reference
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
Pin Assignment
12 11 10 9
QB0 13
8 VREF
nQB0 14
7 nPCLKA
QB1 15
6 PCLKA
nQB1 16
5 VCC
123 4
IDT8SLVP2102I
16-Lead VFQFN
3.0mm x 3.0mm x 0.925mm package body
NL Package
Top View
IDT8SLVP2102ANLGI REVISION B FEBRUARY 26, 2014
1
©2014 Integrated Device Technology, Inc.
1 page  
IDT8SLVP2102I Data Sheet
LOW PHASE NOISE, DUAL 1-TO-2, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER
AC Electrical Characteristics
Table 4A. AC Electrical Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
PCLKA,
fREF
Input
nPCLKA;
Frequency PCLKB,
nPCLKB
V/t
Input
Edge Rate
PCLKA,
nPCLKA;
PCLKB,
nPCLKB
1.5
tPD
tsk(o)
Propagation Delay;
NOTE 1
Output Skew; NOTE 2, 3
PCLKA, nPCLKA to any
QAx, nQAx or PCLKB, nPCLKB to any
QBx, nQBx for VPP = 0.1V or 0.3V
40
135
5
tsk(b)
Bank Skew; NOTE 3, 4
3
tsk(p)
tsk(pp)
Pulse Skew
Part-to-Part Skew;
NOTE 3, 5
fREF = 100MHz
10
100
tJIT, SP
Spurious Suppression,
Coupling from QA0 to
QB0
Channel_ISOL Channel Isolation
tR / tF
Output Rise/ Fall Time
VPP
Peak-to-Peak Input
Voltage; NOTE 6, 8
VCMR
Common Mode Input
Voltage; NOTE 6, 7, 8
fQB0 = 500MHz, VPP(PCLKB) = 0.15V,
VCMR(PCLKB) = 1V and
fQA0 = 62.5MHz, VPP(PCLKA) = 1V,
VCMR(PCLKA) = 1V
fQB0 = 500MHz, VPP(PCLKB) = 0.15V,
VCMR(PCLKB) = 1V and
fQA0 = 15.625MHz, VPP(PCLKA) = 1V,
VCMR(PCLKA) = 1V
fREF = 122.88MHz
20% to 80%
fREF < 1.5GHz
fREF > 1.5GHz
25
0.1
0.2
1.0
-58
-70
65
90
VO(pp)
VDIFF_OUT
Output Voltage Swing,
Peak-to-Peak
Differential Output
Voltage Swing,
Peak-to-Peak
VCC = 3.3V, fREF 2GHz
VCC = 2.5V, fREF 2GHz
VCC = 3.3V, fREF 2GHz
VCC = 2.5V, fREF 2GHz
0.40 0.60
0.35 0.55
0.80 1.2
0.70 1.1
Maximum
2
225
15
10
25
175
140
1.5
1.5
VCC – 0.6
1.0
1.0
20
2.0
Units
GHz
V/ns
ps
ps
ps
ps
ps
dB
dB
dB
ps
V
V
V
V
V
V
V
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crosspoint.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoints.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew within a bank with equal load conditions. Measured at the differential crosspoints.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoints.
NOTE 6: VIL should not be less than -0.3V. VIH should not be higher than VCC.
NOTE 7: Common mode input voltage is defined at the crosspoint.
NOTE 8: For single-ended LVCMOS input applications, please refer to the Applications Information, Wiring the Differential Input to accept
single-ended levels, Figures 1A and 1B.
IDT8SLVP2102ANLGI REVISION B FEBRUARY 26, 2014
5
©2014 Integrated Device Technology, Inc.
5 Page 
IDT8SLVP2102I Data Sheet
LOW PHASE NOISE, DUAL 1-TO-2, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER
Recommendations for Unused Input and Output Pins
Inputs:
PCLK/nPCLK Inputs
For applications not requiring the use of a differential input, both the
PCLK and nPCLK pins can be left floating. Though not required, but
for additional protection, a 1k resistor can be tied from PCLK to
ground.
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
IDT8SLVP2102ANLGI REVISION B FEBRUARY 26, 2014
11
©2014 Integrated Device Technology, Inc.
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet IDT8SLVP2102I.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| IDT8SLVP2102I | LVPECL Output Fanout Buffer | IDT |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |