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PDF IDT8SLVP1102I Data sheet ( Hoja de datos )
| Número de pieza | IDT8SLVP1102I | |
| Descripción | LVPECL Output Fanout Buffer | |
| Fabricantes | IDT | |
| Logotipo |  |
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Low Phase Noise, 1-to-2, 3.3V, 2.5V
LVPECL Output Fanout Buffer
IDT8SLVP1102I
DATASHEET
General Description
The IDT8SLVP1102I is a high-performance differential LVPECL
fanout buffer. The device is designed for the fanout of high-frequency,
very low additive phase-noise clock and data signals. The
IDT8SLVP1102I is characterized to operate from a 3.3V or 2.5V
power supply. Guaranteed output-to-output and part-to-part skew
characteristics make the IDT8SLVP1102I ideal for those clock
distribution applications demanding well-defined performance and
repeatability. One differential input and two low skew outputs are
available. The integrated bias voltage reference enables easy
interfacing of single-ended signals to the device input. The device is
optimized for low power consumption and low additive phase noise.
Features
• Two low skew, low additive jitter LVPECL output pairs
• Differential PCLK, nPCLK pair can accept the following differential
input levels: LVDS, LVPECL, CML
• Maximum input clock frequency: 2GHz
• Output skew: 5ps (typical)
• Propagation delay: 250ps (maximum)
• Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V,
12kHz - 20MHz: 49fs (maximum)
• Full 3.3V or 2.5V supply voltage
• Maximum device current consumption (IEE): 34mA (maximum)
• Available in lead-free (RoHS 6), 16-Lead VFQFN package
• -40°C to 85°C ambient operating temperature
• Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can also
accept single-ended LVCMOS levels. See Applications section
Wiring the Differential Input Levels to Accept Single-ended Levels
(Figure 1A and Figure 1B)
Block Diagram
VCC
PCLK
nPCLK
VREF
Voltage
Reference
Q0
nQ0
Q1
nQ1
Pin Assignment
16 15 14 13
VEE 1
12 nQ1
nc 2
11 Q1
nc 3
10 nQ0
nc 4
9 Q0
5 6 78
IDT8SLVP1102I
16-Lead VFQFN
3.0mm x 3.0mm x 0.925mm package body
NL Package
Top View
IDT8SLVP1102ANLI REVISION A FEBRUARY 25, 2014
1
©2014 Integrated Device Technology, Inc.
1 page  
IDT8SLVP1102I Data Sheet
LOW PHASE NOISE, 1-TO-2, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER
AC Electrical Characteristics
Table 4. AC Electrical Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical
fREF
Input Frequency
PCLK,
nPCLK
V/t
Input Edge Rate
PCLK,
nPCLK
1.5
tPD
tsk(o)
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 3
PCLK, nPCLK to any Qx, nQx
for VPP = 0.1V or 0.3V
70 140
5
tsk(p)
tsk(pp)
Output Pulse Skew
Part-to-Part Skew; NOTE 3, 4
fREF = 100MHz
6
80
fREF = 122.88MHz Sine Wave, VPP = 1V,
Integration Range: 1kHz – 40MHz
157
fREF = 122.88MHz Sine Wave, VPP = 1V,
Integration Range: 10kHz – 20MHz
92
fREF = 122.88MHz Sine Wave, VPP = 1V,
Integration Range: 12kHz – 20MHz
91
fREF = 156.25MHz Square Wave, VPP = 1V,
Integration Range: 1kHz – 40MHz
tJIT
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
fREF = 156.25MHz Square Wave, VPP = 1V,
Integration Range: 10kHz – 20MHz
fREF = 156.25MHz Square Wave, VPP = 1V,
Integration Range: 12kHz – 20MHz
38
36
36
fREF = 156.25MHz Square Wave, VPP = 0.5V,
Integration Range: 1kHz – 40MHz
60
fREF = 156.25MHz Square Wave, VPP = 0.5V,
Integration Range: 10kHz – 20MHz
49
fREF = 156.25MHz Square Wave, VPP = 0.5V,
Integration Range: 12kHz – 20MHz
49
tR / tF
VPP
VCMR
Output Rise/ Fall Time
Peak-to-Peak Input Voltage;
NOTE 5, 7
Common Mode Input
Voltage; NOTE 5, 6, 7
20% to 80%
fREF < 1.5GHz
fREF > 1.5GHz
35 110
0.1
0.2
1.0
VO(pp)
Output Voltage Swing,
Peak-to-Peak
VDIFF_OUT
Differential Output Voltage
Swing, Peak-to-Peak
VCC = 3.3V, fREF 2GHz
VCC = 2.5V, fREF 2GHz
VCC = 3.3V, fREF 2GHz
VCC = 2.5V, fREF 2GHz
0.45 0.75
0.4 0.65
0.9 1.5
0.8 1.3
Maximum Units
2 GHz
V/ns
250 ps
15 ps
10 ps
230 ps
fs
fs
fs
51 fs
49 fs
49 fs
77 fs
63 fs
63
180
1.5
1.5
VCC – 0.6
1.0
1.0
2.0
2.0
fs
ps
V
V
V
V
V
V
V
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crosspoint.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoints.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoints.
NOTE 5: VIL should not be less than -0.3V. VIH should not be higher than VCC.
NOTE 6: Common mode input voltage is defined as the crosspoint.
NOTE 7: For single-ended LVCMOS input applications, please refer to the Applications Information, Wiring the Differential Input to accept
single-ended levels, Figures 1A and 1B.
IDT8SLVP1102ANLI REVISION A FEBRUARY 25, 2014
5
©2014 Integrated Device Technology, Inc.
5 Page 
IDT8SLVP1102I Data Sheet
LOW PHASE NOISE, 1-TO-2, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER
3.3V LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, LVDS, CML and other
differential signals. Both signals must meet the VPP and VCMR input
requirements. Figures 2A to 2E show interface examples for the
PCLK/ nPCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
3.3V
CML
3.3V
3.3V
PCLK
nPCLK
LVPECL
Input
3.3V
o = 50Ω
CML Built-In Pullup
o = 50Ω
R1
100Ω
3.3V
PCLK
nPCLK
LVPECL
Input
Figure 2A. PCLK/nPCLK Input Driven by a CML Driver
Figure 2B. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
3.3V
LVPECL
o = 50Ω
o = 50Ω
3.3V
R3
125Ω
R4
125Ω
3.3V
PCLK
nPCLK
LVPECL
R1 R2
84Ω 84Ω
Input
Figure 2C. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver
Figure 2D. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver with AC Couple
3.3V
LVDS
Zo = 50
Zo = 50
3.3V
R1
100
PCLK
nPCLK
LVPECL
Input
Figure 2E. PCLK/nPCLK Input Driven by a
3.3V LVDS Driver
IDT8SLVP1102ANLI REVISION A FEBRUARY 25, 2014
11
©2014 Integrated Device Technology, Inc.
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet IDT8SLVP1102I.PDF ] | |
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