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PDF IDT8SLVD1208I Data sheet ( Hoja de datos )
| Número de pieza | IDT8SLVD1208I | |
| Descripción | LVDS Output Fanout Buffer | |
| Fabricantes | IDT | |
| Logotipo |  |
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1:8, LVDS Output Fanout Buffer
IDT8SLVD1208I
DATA SHEET
General Description
The IDT8SLVD1208I is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The
IDT8SLVD1208I is characterized to operate from a 2.5V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the IDT8SLVD1208I ideal for those clock
distribution applications demanding well-defined performance and
repeatability. Two selectable differential inputs and eight low skew
outputs are available. The integrated bias voltage reference enables
easy interfacing of single-ended signals to the device inputs. The
device is optimized for low power consumption and low additive
phase noise.
Features
• Eight low skew, low additive jitter LVDS output pairs
• Two selectable, differential clock input pairs
• Differential PCLK, nPCLK pairs can accept the following
differential input levels: LVDS, LVPECL
• Maximum input clock frequency: 2GHz (maximum)
• LVCMOS/LVTTL interface levels for the control input (input select)
• Output skew: 8ps (typical)
• Propagation delay: 255ps (typical)
• Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V,
10kHz - 20MHz: 65fs (typical)
• Maximum device current consumption (IDD): 170mA
• 2.5V supply voltage
• Lead-free (RoHS 6), 28-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature
Pin Assignment
Q4 22
nQ4 23
Q5 24
nQ5 25
Q6 26
nQ6 27
VDD 28
14 GND
13 nQ0
12 Q0
11 VREF0
10 nPCLK0
9 PCLK0
8 VDD
IDT8SLVD1208NBGI REVISION A MAY 1, 2013
IDT8SLVD1208I
28 lead VFQFN
5.0mm x 5.0mm x 0.925mm package body
Pad size 3.25mm x 3.25 mm
NB Package
Top View
1 ©2013 Integrated Device Technology, Inc.
1 page  
IDT8SLVD1208I Data Sheet
1:8, LVDS OUTPUT FANOUT BUFFER
Table 4C. Differential Inputs Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
PCLK0,
IIH
Input High Current
nPCLK0
PCLK1,
nPCLK1
VIN = VDD = 2.625V
PCLK0,
PCLK1
IIL Input Low Current
nPCLK0,
nPCLK1
VIN = 0V, VDD = 2.625V
VIN = 0V, VDD = 2.625V
-10
-150
VREF0,
VREF1
VPP
VCMR
Reference Voltage for Input Bias
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
IREFx = ±1mA
fREF < 1.5GHz
fREF > 1.5GHz
VDD – 1.5
0.1
0.2
1.0
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined at the crosspoint.
Typical
Maximum Units
150 µA
µA
µA
VDD – 1.25
VDD – 1.15
1.5
1.5
VDD – 0.6
V
V
V
V
Table 4D. LVDS DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VOD
VOD
Differential Output Voltage
VOD Magnitude Change
outputs loaded with 100
247
VOS
VOS
Offset Voltage
VOS Magnitude Change
1.125
Typical
Maximum
454
50
1.55
50
Units
mV
mV
V
mV
IDT8SLVD1208NBGI REVISION A MAY 1, 2013
5
©2013 Integrated Device Technology, Inc.
5 Page 
IDT8SLVD1208I Data Sheet
1:8, LVDS OUTPUT FANOUT BUFFER
Parameter Measurement Information, continued
nPCLK0
PCLK0
nPCLK1
PCLK1
nQ[0:7]
Q[0:7]
Input Skew
tPD2
tPD1
tsk(i)
tsk(i) = |tPD1 - tPD2|
Spectrum of Output Signal Q
A0 MUX selects active
input clock signal
MUX_ISOL = A0 – A1
A1 MUX selects other input
MUX Isolation
ƒ
(fundamental)
Frequency
nPCLK[0:1]
PCLK[0:1]
nQ[0:7]
Q[0:7]
tPD
Propagation Delay
Offset Voltage Setup
Differential Output Voltage Setup
IDT8SLVD1208NBGI REVISION A MAY 1, 2013
11
©2013 Integrated Device Technology, Inc.
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet IDT8SLVD1208I.PDF ] | |
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