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PDF ICS8S89874I Data sheet ( Hoja de datos )
| Número de pieza | ICS8S89874I | |
| Descripción | 1:2 Differential-to-LVPECL Buffer/Divider | |
| Fabricantes | IDT | |
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1:2 Differential-to-LVPECL Buffer/Divider
ICS8S89874I
DATA SHEET
General Description
The ICS8S89874I is a high speed 1:2 Differential-to- LVPECL Buffer/
Divider. The ICS8S89874I has a selectable ÷1, ÷2, ÷4, ÷8, ÷16
output divider, which allows the device to be used as either a 1:2
fanout buffer or frequency divider. The clock input has internal
termination resistors, allowing it to interface with several differential
signal types while minimizing the number of required external
components. The device is packaged in a small, 3mm x 3mm
VFQFN package, making it ideal for use on space-constrained
boards.
Features
• Two LVPECL/ECL output pairs
• Frequency divide select options: ÷1 (pass through), ÷2, ÷4, ÷8,
÷16
• IN, nIN input can accept the following differential input levels:
LVPECL, LVDS, CML
• Output frequency: 2GHz (maximum)
• Output skew: 15ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Additive phase jitter, RMS: 0.20ps (typical)
• LVPECL supply voltage range: 2.375V to 3.63V
• ECL supply voltage range: -3.63V to -2.375V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
S2 Pullup
nRESET Pullup
Enable
FF
Enable
MUX
IN
50Ω
VT
50Ω
nIN
S0 Pullup
S1 Pullup
Decoder
VREF_AC
00 ÷2
01 ÷4
10 ÷8
11 ÷16
0
1
Pin Assignment
16 15 14 13
Q0 1
12 IN
nQ0 2
11 VT
Q1 3
10 VREF_AC
Q0
nQ1 4
9 nIN
56 78
nQ0
Q1
nQ1 ICS8S89874I
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
K Package
Top View
ICS8S89874BKI REVISION A OCTOBER 22, 2010
1
©2010 Integrated Device Technology, Inc.
1 page  
ICS8S89874I Data Sheet
1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER
Table 4C. Differential DC Characteristics, VCC = 3.3V ± 10% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
RIN
VIH
VIL
VIN
VDIFF_IN
IIN
VREF_AC
Differential Input Resistance (IN, nIN)
Input High Voltage
(IN, nIN)
Input Low Voltage
(IN, nIN)
Input Voltage Swing
Differential Input Voltage Swing
Input Current; NOTE 1
(IN, nIN)
Bias Voltage
40
1.2
0
0.15
0.3
VCC – 1.45
50
VCC – 1.37
60
VCC
VIH – 0.15
1.2
35
VCC – 1.32
NOTE 1: Guaranteed by design.
Units
Ω
V
V
V
V
mA
V
Table 4D. LVPECL DC Characteristics, VCC = 3.3V ± 10% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
VOH
VOL
VOUT
VDIFF_OUT
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Voltage Swing
Differential Output Voltage Swing
VCC – 1.175
VCC – 2.0
0.6
1.2
VCC – 0.82
VCC – 1.575
1.0
2.0
NOTE: Input and output parameters vary 1:1 with VCC.
NOTE 1: Outputs terminated with 50Ω to VCC – 2V.
Units
V
V
V
V
ICS8S89874BKI REVISION A OCTOBER 22, 2010
5
©2010 Integrated Device Technology, Inc.
5 Page 
ICS8S89874I Data Sheet
1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins has internal pullups; additional resistance is not
required but can be added for additional protection. A 1kΩ resistor
can be used.
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
3.3V
Zo = 50Ω
3.3V
+
LVPECL
Zo = 50Ω
R1
50Ω
RTT =
1
((VOH + VOL) / (VCC – 2)) – 2
* Zo
_
Input
R2
50Ω
VCC - 2V
RTT
Figure 4A. 3.3V LVPECL Output Termination
3.3V
LVPECL
3.3V
R3 R4
125Ω
125Ω
3.3V
Zo = 50Ω
+
Zo = 50Ω
R1
84Ω
_
R2
84Ω
Input
Figure 4B. 3.3V LVPECL Output Termination
ICS8S89874BKI REVISION A OCTOBER 22, 2010
11
©2010 Integrated Device Technology, Inc.
11 Page | ||
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| PDF Descargar | [ Datasheet ICS8S89874I.PDF ] | |
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