S6E2D55J0A Datasheet PDF - Cypress Semiconductor
| Part Number | S6E2D55J0A | |
| Description | Microcontroller | |
| Manufacturers | Cypress Semiconductor | |
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S6E2D5 Series
32-bit ARM® Cortex®-M4F
FM4 Microcontroller
Devices in the S6E2D5 Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This series
is based on the ARM Cortex-M4F Processor with on-chip Flash memory and SRAM. The series has peripheral functions such as
graphics engine, display controller, motor control timers, ADCs, and Communication Interfaces (USB, CAN, UART, CSIO, I2C, LIN).
The products that are described in this data sheet are TYPE4-M4 category products. See the FM4 Family Peripheral Manual Main
Part (002-04856).
Features
32-bit ARM Cortex-M4F Core
Processor version: r0p1
Up to 160 MHz frequency operation
Built-in FPU
Supports DSP instructions
Memory Protection Unit (MPU): improves the reliability of an
embedded system
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 128 peripheral interrupts
and 16 priority levels
24-bit system timer (Sys Tick): System timer for OS task
management
On-Chip Memories
Flash memory
This series has on-chip flash memory with these features:
384 Kbytes
Built-in Flash Accelerator System with 16 Kbytes trace
buffer memory
Security function for code protection
Notes:
• The read access to flash memory can be achieved
without wait-cycle up to operation frequency of 72 MHz.
• Even at the operation frequency more than 72 MHz, an
equivalent access to flash memory can be obtained by
Flash Accelerator System.
SRAM
This is composed of two independent SRAMs (SRAM0 and
SRAM2). SRAM0 is connected to I-code bus and D-code bus
of Cortex-M4F core. SRAM2 is connected to the system bus of
Cortex-M4F core.
SRAM0: 32 Kbytes
SRAM2: 4 Kbytes
VRAM
This series is equipped with a SRAM for GDC.
Max 512 Kbytes
VFLASH
S6E2D55GJA is equipped with a Flash for GDC.
2 Mbytes
External Bus Interface
Supports SRAM, NOR, NAND Flash and SDRAM devices
Up to two chip selects CS0 and CS8 (CS8 is only for
SDRAM)
8-/16-bit data width
Up to 25-bit address bit
Maximum area size : Up to 256 Mbytes
Supports address/data multiplexing
Supports external RDY function
Supports the scramble function
Possible to set the validity/invalidity of the scramble
function for the external areas 0x6000_0000 to
0x7FFF_FFFF in 4 Mbytes units.
Possible to set two kinds of the scramble key.
Note: It is necessary to prepare the dedicated software
library to use the scramble function.
USB Interface (One channel)
A USB interface is composed of device and host.
USB device
USB2.0 Full-Speed supported
Max 6 EndPoint supported
• EndPoint 0 is for control transfer
• EndPoint 1, 2 can be selected for bulk-transfer,
interrupt-transfer or isochronous-transfer
• EndPoint 3 to 5 can select bulk-transfer or
interrupt-transfer
EndPoint 1 to 5 comprise the double buffer
The size of each endpoint is as follows.
• Endpoint 0, 2 to 5: 64 bytes
• EndPoint 1: 256 bytes
USB host
USB2.0 Full-Speed / Low-Speed supported
Bulk-transfer, interrupt-transfer and isochronous-transfer
support
USB device connected/disconnected automatically detect
In/out token handshake packet automatically accepted
Max 256-byte packet-length supported
Wake-up function supported
Cypress Semiconductor Corporation
Document Number: 002-03982 Rev.*B
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised March 4, 2016
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S6E2D5 Series
Table of Contents
Features................................................................................................................................................................................... 1
1. Product Lineup.................................................................................................................................................................. 7
2. Packages ........................................................................................................................................................................... 8
3. Pin Assignment ................................................................................................................................................................. 9
4. Pin Descriptions.............................................................................................................................................................. 13
5. I/O Circuit Type................................................................................................................................................................ 47
6. Handling Precautions ..................................................................................................................................................... 54
6.1 Precautions for Product Design ................................................................................................................................... 54
6.2 Precautions for Package Mounting.............................................................................................................................. 55
6.3 Precautions for Use Environment ................................................................................................................................ 57
7. Handling Devices ............................................................................................................................................................ 58
8. Block Diagram ................................................................................................................................................................. 61
9. Memory Size .................................................................................................................................................................... 62
10. Memory Map .................................................................................................................................................................... 62
11. Pin Status in Each CPU State ........................................................................................................................................ 64
12. Electrical Characteristics ............................................................................................................................................... 72
12.1 Absolute Maximum Ratings......................................................................................................................................... 72
12.2 Recommended Operating Conditions.......................................................................................................................... 73
12.3 DC Characteristics....................................................................................................................................................... 77
12.3.1 Current Rating.............................................................................................................................................................. 77
12.3.2 Pin Characteristics ....................................................................................................................................................... 87
12.4 AC Characteristics....................................................................................................................................................... 88
12.4.1 Main Clock Input Characteristics.................................................................................................................................. 88
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 89
12.4.3 Built-in CR Oscillation Characteristics.......................................................................................................................... 89
12.4.4 Operating Conditions of Main PLL (In the Case of Using Main Clock for Input Clock of PLL)...................................... 90
12.4.5 Operating Conditions of USB/I2S/GDC PLL (In the Case of Using Main Clock for Input Clock of PLL) ....................... 90
12.4.6 Operating Conditions of Main PLL (In the Case of Using Built-in High-Speed CR Clock for Input Clock
of Main PLL)................................................................................................................................................................. 91
12.4.7 Reset Input Characteristics .......................................................................................................................................... 91
12.4.8 Power-on Reset Timing................................................................................................................................................ 92
12.4.9 GPIO Output Characteristics........................................................................................................................................ 92
12.4.10 External Bus Timing.................................................................................................................................................. 93
12.4.11 Base Timer Input Timing......................................................................................................................................... 104
12.4.12 CSIO Timing ........................................................................................................................................................... 105
12.4.13 External Input Timing.............................................................................................................................................. 138
12.4.14 Quadrature Position/Revolution Counter Timing .................................................................................................... 139
12.4.15 I2C Timing............................................................................................................................................................... 142
12.4.16 ETM Timing ............................................................................................................................................................ 143
12.4.17 JTAG Timing........................................................................................................................................................... 145
12.4.18 I2S Timing ............................................................................................................................................................... 146
12.4.19 GDC:Panel Output Timing ...................................................................................................................................... 151
12.4.20 GDC: SDRAM-IF Timing......................................................................................................................................... 152
12.4.21 GDC: High-Speed Quad SPI Timing....................................................................................................................... 154
12.4.22 GDC: HyperBus I/F Timing ..................................................................................................................................... 156
12.5 12-bit A/D Converter.................................................................................................................................................. 158
Document Number: 002-03982 Rev.*B
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