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PDF BD81010MUV Data sheet ( Hoja de datos )
| Número de pieza | BD81010MUV | |
| Descripción | Gamma voltage generated IC | |
| Fabricantes | ROHM Semiconductor | |
| Logotipo |  |
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Datasheet
Power Supply IC Series for TFT-LCD Panels
Gamma voltage generated IC
with built-in DAC
BD81010MUV
General Description
The feature of gamma voltage generated IC
BD81010MUV provides a single-chip solution with a
high-precision 10-bit DAC setting controlled by I2C serial
communications interface, a buffer amp (14ch), and a
operational amplifier for HVDD (1ch).
Key Specifications
Power Supply Voltage Range(VDD): 2.1V to 3.6V
Power Supply Voltage Range(VCC): 8.0V to 18.0V
Operating Temperature Range:
-40°C to +85°C
Package
W(Typ) x D(Typ) x H(Max)
Features
Single-chip Design means Fewer Components
Built in 10bit DAC (14ch)
Built in DAC Output Buffer Amplifier (14ch)
Built in Operation Amplifier (1ch) for HVDD
I2C Interface ( SDA, SCL )
Thermal Shutdown Circuit
Under-voltage Lockout Protection Circuit
Power ON Reset Circuit
Input Tolerant ( SDA, SCL, EN )
Applications
It may be used with TFT-LCD panels, such as big screen
and high resolution LCD televisions.
VQFN032V5050
5.00mm x 5.00mm x 1.00mm
○Product structure：Silicon monolithic integrated circuit
www.rohm.com
© 2016 ROHM Co., Ltd. All rights reserved.
TSZ22111・14・001
○This product has no designed protection against radioactive rays
1/18
TSZ02201-0313AAF00360-1-2
19.Feb.2016 Rev.001
1 page  
BD81010MUV
Electrical Characteristics (Unless otherwise noted, Ta25°C, VDD=3.3V, VCC=15.0V, VREFIN=5.0V )
Parameter
Symbol
MIN
Limit
TYP
MAX
Unit
Condition
【 Regulator (VDAC) 】
FB Voltage
VFB 0.492 0.500 0.508 V
Input Bias Current
IFB -1.2 0.0 1.2 µA VFB=0.60V
Current Capability
【 Gamma Amplifier 】
IO 10 50
- mA
Sink Current Capability
Nch Side (AMP0)
during REG0=3BBh (14.0V ) setting,
IooA
-
-10.0
-6.6 mA
OUT0=15V input
Sink Current Capability
Nch Side (AMP1 to AMP12)
IooB
-
during REG1 to REG12=199h (6.0V) setting,
-30 -20 mA
OUT1to OUT12=7V input
Sink Current Capability
Nch Side (AMP13)
IooC
-
during REG13=043h (1.0V) setting,
-60 -40 mA
OUT13=2V input
Source Current Capability
Pch Side (AMP0)
IoiA 40
60
during REG0=3BBh (14.0V) setting,
- mA
OUT0=13V input
Source Current Capability
Pch Side (AMP1 to AMP12)
IoiB
20
30
- mA during REG1 to REG12=199h (6.0V) setting,
OUT1to OUT12=5V
Source Current Capability
Pch Side (AMP13)
IoiC 6.6 10.0
- mA during REG13=043h (1.0V) setting,
OUT13=0V input
Load Stability (OUT0)
⊿VO-A
-
10 70 mV IO=0mA to -30mA
REG0=199h (6.0V) setting
Load Stability
(OUT1 to OUT12)
⊿VO-B
-
10 70 mV IO=-15mA to 15mA
REG1 to REG12=199h (6.0V) setting
Load Stability (OUT13)
⊿VO-C
-
10 70 mV IO=0mA to 30mA
REG13=199h (6.0V) setting
MAX Output Voltage (OUT0) VOH-A VCC-0.20 VCC-0.10
-
V IO=-30mA
MAX Output Voltage
(OUT1 to OUT12)
VOH-B VCC-1.00 VCC-0.50
-
V IO=-15mA
MAX Output Voltage (OUT13) VOH-C VCC-0.60 VCC-0.30
-
V IO=-5mA
MIN Output Voltage (OUT0) VOL-A
-
0.30
0.60
V IO=5mA
MIN Output Voltage
(OUT1 to OUT12)
VOL-B
-
0.60
1.20
V IO=15mA
MIN Output Voltage (OUT13) VOL-C
-
0.10
0.20
V IO=30mA
Slew Rate (AMP0)
SR-A
1
4
- V/µsec OUT0=No-load
Slew Rate (AMP1 to OUT12) SR-B
1
4
- V/µsec OUT1 to OUT12= No-load
Slew Rate (AMP13)
SR-C
1
4
- V/µsec OUT13= No-load
【 10 Bit DAC 】
Resolution
RES
-
10
- Bit
Integral Non-linearity Error
00Ah to 3F5h is the allowable margin of
LE -2 - +2 LSB
(INL)
error against the ideal linear.
Differential Non-linearity Error
00Ah to 3F5h is the allowable margin of error
DLE -2 - +2 LSB
(DNL)
against the ideal increase of 1LSB.
www.rohm.com
© 2016 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
5/18
TSZ02201-0313AAF00360-1-2
19.Feb.2016 Rev.001
5 Page 
BD81010MUV
・I2C Timing
SCL
SDA
(IN)
SDA
(OUT)
tHD:STA
tBUF
tR
tF
tHIGH
tSU;DAT
tLOW
tPD
tHD;DAT
tDH
SCL
tSU;STA
tHD;STA
tSU;STO
SDA
S
tl S：START bit
P P：STOP bit
・Timing regulation
Figure 5. Timing
Parameter
SCL Frequency
SCL”H” time
SCL”L” time
Rise time
Fall time
Start condition holding time
Start condition setup time
SDA Holding time
SDA Setup time
Acknowledge delay time
Acknowledge holding time
Stop condition setup time
BUS open time
Noise spike width
・Buffer output setting
Symbol
fSCL
tHIGH
tLOW
tR
tF
tHD;STA
tSU;STA
tHD;DAT
tSU;DAT
tPD
tDH
tSU;STO
tBUF
tl
FAST mode
MIN TYP MAX
- - 400
0.6 -
-
1.2 -
-
- - 0.3
- - 0.3
0.6 -
-
0.6 -
-
100 -
-
100 -
-
- - 0.9
- 0.1 -
0.6 -
-
1.2 -
-
- 0.1 -
Unit
kHz
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
µs
The relation between buffer output voltage (OUT0 to OUT13) and DAC setting value is shown below.
Output voltage (OUT0 to OUT13) DAC setting value 1 3 REFIN
1024
Buffer output terminals OUT0 to OUT13 output after UVLO release of VCC. While UVLO detection, the output is HiZ.
www.rohm.com
© 2016 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
11/18
TSZ02201-0313AAF00360-1-2
19.Feb.2016 Rev.001
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet BD81010MUV.PDF ] | |
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