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PDF DM9801A Data sheet ( Hoja de datos )
| Número de pieza | DM9801A | |
| Descripción | 1M Home Phoneline Network Physical Layer Single Chip Transceiver | |
| Fabricantes | Davicom | |
| Logotipo |  |
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DM9801A
1M Home Phoneline Network Physical Layer Single Chip Transceiver
General Description
The DM9801A is a physical-layer, single-chip, low-power
transceiver for 1M Home Phoneline Network applications.
On the media side, it provides an interface to a Home
Phoneline wiring system. The reconciliation layer interfaces
to the DM9801A either through an IEEE802.3u subset
Media Independent Interface (MII) or a pseudo-standard
General Purpose Serial Interface (GPSI). A management
interface is provided by MDIO/MDC when operating in MII
mode, or a Serial Peripheral Interface bus when operating in
GPSI mode.
The DM9801A uses a low-power and high-performance
CMOS process. It contains the entire physical layer
functions of 1M as defined by Home Phoneline Network
Alliance, Rev. 1.1, including the Physical Coding Sublayer,
(RLL25) Encoder/Decoder (ENC/DEC), 4-wire HN Driver
circuit and receiver analog front end (AFE).
Patent-Pending Circuitry Includes:
Enhanced 4-wire Home Network transceiver circuit.
Compatible with HomePNA 1M PHY specification version
1.1 and HomePNA certification document version 1.0
Block Diagram
GPSI - MII
Transmit
GPSI - MII
Receive
Muxed
GPSI
or Mii
Interface
RLL25
Encoder
Master
PHY
Controller
Transmit
Timing
Generator
HN
Secondary
Driver
HNB+/-
HN
Primary
Driver
HNA+/-
Interface
Select
RLL25
Decoder
Receiever
and
Digital PLL
Receiver
AFE
Final
Version: DM9801A-DS-F01
May 30, 2001
1
1 page  
DM9801A
1M Home Phoneline Network Physical Layer Single Chip Transceiver
Pin Description (Continued)
Pin No. Pin Name I/O
Description
Station Interface: Receive Data, Transmit Data and Management (Continued)
67
MDIO
I/O,Z MII Serial Management Data (MII Mode, INTFSEL = 0):
Or Bi-directional management instruction/data signal that may be driven by the
SCS#
station management entity or the PHY. This pin requires a 1.5KΩ pull-up
resistor.
Serial Interface Chip Select (GPSI Mode, INTFSEL = 1):
SCS# is a bi-directional management chip select signal that may be driven
by the station management entity or the PHY. (Active low)
97
RXD0
O,Z Receive Data Bit 0 (MII Mode, INTFSEL = 0):
Or Receive data output pin, bit 0, for nibble data to the MII
SRXDAT
Serial Receive Data Bit (GPSI Mode, INTFSEL = 1):
Receive data output pin for serial data to the GPSI.
96
RXD1
O,Z Receive Data Bit 1:
Receive data output pin, bit 1, for nibble data to the
95
RXD2
O,Z Receive Data Bit 2:
Receive data output pin, bit 2, for nibble data to the MII
94
RXD3
O,Z Receive Data Bit 3:
Receive data output pin, bit 3, for nibble data to the MII
90 RX_CLK O,Z MII Receive Clock (MII Mode, INTFSEL = 0):
Or RX_CLK is an output pin from the DM9801A. Used as the receive data
SRDCLK
reference clock, to clock out nibble data from the MII when in MII interface
mode.
Serial Receive Data Clock (GPSI Mode, INTFSEL = 1):
SRDCLK is an output from the DM9801A. Used as the receive reference
clock to clock out the SRXDATA when in GPSI interface mode.
91
RX_DV
O,Z Receive Data Valid (MII Mode, INTFSEL = 0):
Or RX_DV is asserted high to indicate that valid data is present on RXD[3:0].
SO Serial Data Output (GPSI Mode, INTFSEL = 1):
This is the serial data output pin from the DM9801A for the SPI bus. The
SPI bus operation is only valid if GPSI mode is selected.
93
CRS
O,Z Carrier Sense:
This pin is asserted high to indicate the presence of carrier due to receive
or transmit activities.
92
COL
O,Z Collision Detect MII Mode, INTFSEL = 0):
or COL is asserted high to indicate detection of collision condition.
CLSN
Collision Detect (GPSI Mode, INTFSEL = 1):
CLSN is asserted high to indicate detection of collision condition.
Final
Version: DM9801A-DS-F01
May 30, 2001
5
5 Page 
DM9801A
1M Home Phoneline Network Physical Layer Single Chip Transceiver
MII Interface (continued)
RXD (receive data) is a nibble (4 bits) of data that are
sampled by the reconciliation sublayer synchronously with
respect to RX_CLK. For each RX_CLK period that
RX_DV is asserted, RXD (3:0) are transferred from the
PHY to the MAC reconciliation sublayer.
RX_CLK (receive clock) output to the MAC reconciliation
sublayer is a clock that provides the timing reference for
the transfer of the RX_DV, RXD, and RX_ER signals.
RX_DV (receive data valid) input from the PHY to indicate
the PHY is presenting recovered and decoded nibbles to
the MAC reconciliation sublayer. To interpret a receive
frame correctly by the reconciliation sublayer, RX_DV
must encompass the frame starting no later than the Start-
of-Frame delimiter and excluding any End-Stream
delimiter.
The DM9801A management functions correspond
to MII specification for IEEE 802.3u-1995 (Clause
22) for registers 0 through 6 with vendor-specific
registers 16 through 31.
In read/write operation, the management data frame
is 64-bits long and starts with 32 contiguous logic
one bits (preamble) synchronization clock cycles on
MDC. The Start of Frame Delimiter (SFD) is
indicated by a <01> pattern followed by the
operation code (OP):<10> indicates Read operation
and <01> indicates Write operation. For read
operation, a 2-bit turnaround (TA) filing between
Register Address field and Data field is provided for
MDIO to avoid contention. Following the turnaround
time, 16-bit data is read from or written to the
management registers.
CRS (carrier sense) is asserted by the PHY when either
the transmit or receive medium is non-idle and deasserted
by the PHY when the transmit and receive medium are
idle.
MII Serial Management
The MII serial management interface consists of a
data interface, basic register set, and a serial
management interface to the register set. Through
this interface it is possible to control and configure
multiple PHY devices, get status and error
information, and determine the type and capabilities
of the attached PHY device(s).
Serial Management Interface
The serial control interface uses a simple two-wired
serial interface to obtain and control the status of
the physical layer through the MII interface. The
serial control interface consists of MDC
(Management Data Clock), and MDI/O
(Management Data Input/Output) signals.
The MDIO pin is bi-directional and may be shared
by up to 32 devices.
MII Interface Transmit and Receive Timing Diagram
TX_CLK
TX_EN
TXD
RX_CLK
0
CRS
RXD
0
RX_DV
COL
RX_CLK and TX_CLK are synchronized. All signals are inactive. The period of the two clock is 2333.3 ns.
Idle State
Figure 2
Final
Version: DM9801A-DS-F01
May 30, 2001
11
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