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Número de pieza | DM9006 | |
Descripción | 10/100 Mbps 2-port Ethernet Switch Controller | |
Fabricantes | DAVICOM | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de DM9006 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
No Preview Available ! DAVICOM Semiconductor, Inc.
DM9006
10/100 Mbps 2-port Ethernet Switch Controller
with General Processor Interface
DATA SHEET
Preliminary
Version: DM9006-DS-P01
September 1, 2009
1 page DM9006
2-port Switch with Processor Interface
6.46 Snooping Control Register 1 (78H)............................................................................................................ 31
6.47 Snooping Control Register 2 (79H)............................................................................................................ 31
6.48 Snooping Control Register 3 (7AH) ........................................................................................................... 32
6.49 Snooping Control Register 4 (7BH) ........................................................................................................... 32
6.50 Snooping Control Register 5 (7CH) ........................................................................................................... 32
6.51 MIB Counter Port Index Register (80H) ..................................................................................................... 32
6.52 MIB Counter Data Registers (81H~84H) .................................................................................................... 33
6.53 Port-Based VLAN Mapping Table Registers (B0H~BFH)......................................................................... 34
6.54 TOS Priority Map Registers (C0H~CFH).................................................................................................... 34
6.55 VLAN Priority Map Registers (D0H~D1H) ................................................................................................. 37
6.56 Memory Data Pre-Fetch Read Command without Address Increment Register (F0H) ........................ 37
6.57 Memory Data Read Command with Address Increment Register (F2H)................................................ 37
6.58 Memory Data Read Address Register (F4H) ............................................................................................. 37
6.59 Memory Data Read Address Register (F5H) ............................................................................................. 37
6.60 Memory Data Write Command without Address Increment Register (F6H).......................................... 37
6.61 Memory Data Write Command with Address Increment Register (F8H) ............................................... 38
6.62 Memory Data Write Address Register (FAH) ............................................................................................ 38
6.63 Memory Data Write Address Register (FBH) ............................................................................................ 38
6.64 TX Packet Length Registers (FCH~FDH) .................................................................................................. 38
6.65 Interrupt Status Register (FEH).................................................................................................................. 38
Preliminary datasheet
DM9006-13-DS-P01
September 1, 2009
5
5 Page DM9006
2-port Switch with Processor Interface
3. FEATURES
Ethernet Switch with two 10/100Mb PHY, and a flexible 8-bit or 16-bit general processor
bus interface
Store and Forward switching approach
Support HP Auto-MDIX
Support up-to 1K Unicast MAC addresses
Support IEEE 802.3x Flow Control in Full-duplex mode
Support Back Pressure Flow Control in Half-duplex mode
Per port supports ingress or egress bandwidth rate control
Support Broadcast/Multicast Storm Suppression
Support maximum packet length up to 1536(default)/2032 bytes
Support head of Line (HOL) blocking prevention
Support MIB counters for diagnostic
General processor bus is slave architecture
General processor bus driving capability is adjustable
General processor bus supports TCP/UDP/IPv4 checksum offload
EEPROM interface for power up configuration
Support EEPROM 93C46/93C56 with auto-detecting
Driving capability of TXD/TXE of MII is adjustable
Per port supports 4 level priority queues by Port-based, 802.1p VLAN, and IP TOS priority.
The priority queue can be set at WRR(Weighted Round Robin) or Strictly(High priority
queue first)
Support 802.1Q VLAN up-to 16 VLAN group.
Support VLAN ID tag/untag options
MAC Address Table is accessible
Support 256-entry multicast address table
Support port security function
Support 32 entry hardware-based IGMP Snooping V1, V2
uP data driving capability adjustable
64-pin LQFP 1.8V internal core, 3.3V I/O with 5V tolerant
Support Lead-Free and Halogen–Free
Preliminary datasheet
DM9006-13-DS-P01
September 1, 2009
11
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet DM9006.PDF ] |
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