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PDF BD8118FM Data sheet ( Hoja de datos )
| Número de pieza | BD8118FM | |
| Descripción | White LED Driver IC | |
| Fabricantes | ROHM Semiconductor | |
| Logotipo |  |
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TECHNICAL NOTE
For LCD Panel Backlight Applications
White LED Driver IC
BD8118FM
rev. 1.50
● Outline
BD8118FM is a white LED driver featuring a high input voltage range (36V MAX), an integrated step-up DC/DC converter
and four constant-current output drivers on a single chip. Brightness can be controlled by either PWM or VDAC methods.
● Features
1) Input voltage range4.5 – 30 V
2) Integrated step-up DC/DC controller
3) Four integrated LED current driver channels (150 mA max. each channel)
4) Compatible with PWM light-modulation
0.38 – 99.5%)
5) Built-in protection functions (UVLO, OVP, TSD, OCP)
6) Abnormal status detection function (open)
7) HSOP-M28 package
● Applications
Car navigation system backlights, small/medium-sized LCD panels, etc.
● Absolute maximum ratings (Ta = 25 ͠)
Parameter
Symbol
Rating
Unit
Power supply voltage (Pin 1)
VCC 36
V
Load switch output voltage (Pin 2)
VLOADSW
36
V
LED output voltage (Pin 12,14,15,17)
VLED
36
V
FAIL output voltage (Pin 3,20)
VOL 7
V
Input voltage (Pin 5,6,10,11,24)
VIN -0.3㨪7 < VCC
V
VDAC input voltage (Pin 8)
Power Consumption
VDAC
Pd
-0.3㨪7 < VCC
2.20 ̪1
V
W
Junction temperature
Tjmax
150
͠
Operating temperature range
Topr -40㨪+95
͠
Storage temperature range
LED maximum output current (Pin : 12,14,15,17)
Tstg
ILED
-55㨪+150
150̪̪
͠
mA
̪1 IC mounted on glass epoxy board measuring 70mm×70mm×1.6mm, power dissipated at a rate of 17.6mw/͠ at temperatures above
25͠
̪2 Dispersion figures for LED maximum output current and VF are correlated. Please refer to data on separate sheet.
̪3 Amount of current per channel.
● Operating conditions (Ta = 25 ͠)
Parameter
Symbol
Target value
Unit
Power supply voltage (Pin 1)
VCC 4.5㨪30
V
Oscillating frequency range
FOSC
50㨪550
kHz
External synchronization frequency range (Pin 6) ̪̪ FSYNC
fosc㨪550
kHz
External synchronization pulse duty range (Pin 6)
FSDUTY
40㨪60
%
̪4 Connect SYNC to GND when not using external frequency synchronization.
̪5 Do not switch between internal and external synchronization when an external synchronization signal is input to the device.
October. 2008
ROHM Co., Ltd.
1 page  
● 5V voltage reference (VREG)
5V (Typ.) is generated from the VCC input voltage when the enable pin is set high. This voltage is used to power internal
circuitry, as well as the voltage source for device pins that need to be fixed to a logical HIGH.
UVLO protection is integrated into the VREG pin. The voltage regulation circuitry operates uninterrupted for output voltages
higher than 2.9 V (Typ.), but if output voltage drops to 2.8 V (Typ.) or lower, UVLO engages and turns the IC off.
Connect a capacitor (Creg = 10uF Typ.) to the VREG terminal for phase compensation. Operation may become unstable if
Creg is not connected.
● Self-diagnostic functions
The operating status of the internal protection circuitry is transmitted via the FAIL1 and FAIL2 output pins (open drain).
When UVLO, OVP, OCP or TSD protection is engaged, FAIL1 and SWOUT output are pulled low, and step-up DC/DC
conversion is stopped. For OCP, SWOUT is pulled low for only 1 cycle of FOSC, as the protection is activated on a
pulse-by-pulse basis. If UVLO, OVP or TSD protection is engaged, LED output pins are held open (Hi-Z). The TSD, OVP and
OCP functions also serve to protect the VREG terminal. Additionally, FAIL1 and LOADSW outputs are internally inverted;
thus, if FAIL1 engages (i.e. is pulled low), then LOADSW will turn off.
OVP
OCP
TSD
UVLO
FAIL1
OPEN
MASK
EN=OFF
(UVLO)
FAIL2
SQ
R
FAIL2 output is pulled low when an open circuit is detected. The open circuit detection engages via a latch, which is cycled via
the ON/OFF (UVLO) signal from the EN terminal. The device detects an open circuit if the LED output is lower than 0.15V
(Typ.), or if the voltage at the OVP pin reaches 1.7V (Typ.) or more.
FAIL output pins are open-drain, so ensure pull-up resistors are connected to both for proper operation.
LED1 0.8V
GND
Other LED Output
0.8V
0.15V
Step-up Voltage Vout
VFxN+0.8V
OVP
2.0V
1.7V
FAIL2
LED1
LED1
OPEN
OFF
● Constant-current LED drivers
If less than four constant-current drivers are used, unused channels should be switched off via the LEDEN pin configuration.
The truth table for these pins is shown below. If a driver output is enabled but not used (i.e. left open), the IC’s open
circuit-detection circuitry will operate. Do not connect the driver output to GND as the inputs of the error amplifier cannot be
deactivated via the LEDEN pin. Instead, keep the driver output floating or connect it to VREG. The LEDEN terminals are
pulled down internally in the IC, so if left open, the IC will recognize them as logic LO. However, they should be connected
directly to VREG or fixed to a logic HI when in use.
LED EN
ޛ1ޜ ޛ2ޜ
LL
HL
LH
HH
LED
123
ON ON ON
ON ON ON
ON ON OFF
ON OFF OFF
5/16
4
ON
OFF
OFF
OFF
5 Page 
● Timing Chart
VCC
EN
VREG
4.5V
OK to input EN at VCC= 4.5V or greater
2.9V
Internal Signal
UVLO
VDAC
SYNC
PWM
TINON
TPWMON
TPWMON > TINON
TPWMON > 500[V/As] x CREG [sec]
VCC>VREG
2.8V
TPWMOFF > TINOFF
OVP
OCP(CS)
Internal Signal
TSD
Load SW
FAIL1
( 㪜㫏㫋㪼㫉㫅㪸㫃㩷㪧㫌㫃㫃㪄㪬㫇 )
2.0V
1.6V
0.4V
175㷄
150㷄
VREG off
when TSD on
̪Fix LEDEN1 and 2 before input.
Fig.25
11/16
11 Page | ||
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| PDF Descargar | [ Datasheet BD8118FM.PDF ] | |
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