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PDF ICS551 Data sheet ( Hoja de datos )
| Número de pieza | ICS551 | |
| Descripción | 1 TO 4 CLOCK BUFFER | |
| Fabricantes | IDT | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ICS551 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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1 TO 4 CLOCK BUFFER
DATASHEET
ICS551
Description
The ICS551 is a low cost, high-speed single input to
four output clock buffer. Part of IDT’s ClockBlocksTM
family, this is our lowest cost, small clock buffer.
See the ICS552-02B for monolithic dual version of the
ICS551 in a 20 pin QSOP.
IDT makes many non-PLL and PLL based low skew
output devices as well as Zero Delay Buffers to
synchronize clocks. Contact IDT for all of your clocking
needs.
Features
• Low skew (250 ps) outputs
• Pb-free packaging
• Low cost clock buffer
• Packaged in 8-pin SOIC
• Input/Output clock frequency up to 160 MHz
• Non-inverting output clock
• Ideal for networking clocks
• Operating Voltages of 3.3 and 5.0 V
• Output Enable mode tri-states outputs
• Advanced, low power CMOS process
• Commercial and industrial temperature versions
Block Diagram
ICLK
Q1
Q2
Q3
Q4
Output Enable
IDT™ 1 TO 4 CLOCK BUFFER
1
ICS551
REV P 051310
1 page  
ICS551
1 TO 4 CLOCK BUFFER
FAN OUT BUFFER
AC Electrical Characteristics
VDD = 3.3 V ±10%, Ambient Temperature -40 to +85 ° C, unless stated otherwise
Parameter
Symbol
Conditions
Min. Typ.
Input Frequency
0
Output Frequency
15 pF load, Note 4
Output Clock Rise Time
Output Clock Fall Time
Propagation Delay
tOR
tOF
Note 1
0.8 to 2.0 V
2.0 to 0.8 V
135 MHz
24
Output to Output Skew
Note 2 Rising edges at VDD/2
Max.
160
160
1.0
1.0
8
250
Units
MHz
MHz
ns
ns
ns
ps
VDD = 5 V ±10%, Ambient Temperature -40 to +85 ° C, unless stated otherwise
Parameter
Symbol
Conditions
Min.
Input Frequency
0
Output Frequency
15 pF load, Note 4
Output Clock Rise Time
Output Clock Fall Time
Propagation Delay
tOR
tOF
Note 1
0.8 to 2.0 V
2.0 to 0.8 V
135 MHz
1.5
Output to Output Skew
Note 2 Rising edges at VDD/2
Typ.
3
Max.
135
135
1.0
1.0
6
250
Units
MHz
MHz
ns
ns
ns
ps
Notes:
1. With rail to rail input clock.
2. Between any 2 outputs with equal loading.
3. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock
generators.
4. With external series resistor of 33Ω positioned close to each output pin.
Marking Diagram (ICS551MLF)
Marking Diagram (ICS551MLN)
85
85
551MLF
######
YYWW
551MLN
######
YYWW
14
14
IDT™ 1 TO 4 CLOCK BUFFER
5
ICS551
REV P 051310
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet ICS551.PDF ] | |
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