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PDF BD8149MUV Data sheet ( Hoja de datos )
| Número de pieza | BD8149MUV | |
| Descripción | Gamma voltage generated IC | |
| Fabricantes | ROHM Semiconductor | |
| Logotipo |  |
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Power Supply IC Series for TFT-LCD Panels
Gamma voltage generated IC
with built-in DAC
BD8149MUV
No.16035EBT17
●Description
The feature of gamma voltage generated IC BD8149MUV provides a single-chip solution with a high-precision 10-bit DAC
setting controlled by I2C serial communications interface and a Buffer AMP (12ch). EEPROM auto-read function is also
incorporated.
●Features
1) Single-chip design realizes fewer components
2) Built in 10bit DAC
3) Built in DAC output buffer amplifier (12ch)
4) Double Register synchronous switching function (SEL)
5) I2C interface (SDA, SCL)
STANDARD-MODE, FAST-MODE changeable
6) EEPROM auto-read function
7) Thermal Shut Down circuit
8) Under Voltage Lock Out circuit
9) Power ON Reset circuit
10) Input tolerant (SDA, SCL, EN, EN_AR, SEL)
11) VQFN032V5050 package
●Applications
It may be used with TFT-LCD panels, such as big screen and high resolution LCD televisions.
●Absolute Maximum Ratings (Ta=25℃)
PARAMETER
SYMBOL
RATING
UNIT
Power supply voltage1
VDD
4.5 V
Power supply voltage2
VCC
19 V
REFIN voltage
VREFIN
5V
DAC reference voltage
VDAC
7V
SEL, A0, A1, A2
Functional pin voltage
EN, SLAVE/AR
4.5
V
EN_AR
2-lines serial pin voltage
SDA, SCL
4.5
V
Junction voltage
Power dissipation
Tjmax
Pd
150
4560*1
℃
mW
Operating temperature range
Topr
-25～+85
℃
Storage temperature range
Tstg
-55～+150
℃
*1 To use the IC at temperature over 25℃, derate power rating by 19.52mW /℃.
When mounted on a 4-layer glass epoxy board measuring 74.2 x 74.2 x 1.6mm.
www.rohm.com
© 2016 ROHM Co., Ltd. All rights reserved.
1/17
2016.08 - Rev.B
1 page  
BD8149MUV
●Pin Configuration (Top View)
●Block Diagram
Technical Note
24 23 22 21 20 19 18 17
25 16
26 15
27 14
28 13
29 12
30 11
31 10
32 9
1 23 4 5 6 78
EN
SDA
SCL
EN_AR
A0
A1
A2
SLAVE/AR
VDD VCC VCC
FB
VDD
VCC
-
+
REG1
VREF
Power
ON
Reset
UVLO
TSD
Serial
I/F
VDAC
REFIN
REGISTER0
A/B
REFIN
DAC
REGISTER1
A/B
DAC
REGISTER2
A/B
DAC
REGISTER3
A/B
DAC
REGISTER4
A/B
REGISTER5
A/B
REGISTER6
A/B
DAC
DAC
DAC
REGISTER7
A/B
REGISTER8
A/B
REGISTER9
A/B
REGISTER10
A/B
REGISTER11
A/B
DAC
DAC
DAC
DAC
DAC
CTL
VCC
AMP0
X4
AMP1
X4
AMP2
X4
AMP3
X4
AMP4
X4
AMP5
X4
AMP6
X4
AMP7
X4
AMP8
X4
AMP9
X4
AMP10
X4
AMP11
X4
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
DACGND GND
AGND
AGND
SEL
Fig.2 Pin Configuration & Block Diagram
● Pin Location and Function
PIN
PIN NAME FUNCTION
No.
PIN
PIN NAME FUNCTION
No.
1 GND GND input
17 OUT9 Gamma output pin
2 A0 Device address switching pin
18 OUT8 Gamma output pin
3 A1 Word address switching pin
19 OUT7 Gamma output pin
4 A2 Word address switching pin
20 OUT6 Gamma output pin
5 SDA Serial data input pin
21 OUT5 Gamma output pin
6 SCL Serial clock input pin
22 OUT4 Gamma output pin
7 EN VDAC enable pin
23 OUT3 Gamma output pin
8 EN_AR Auto-read enable pin
24 OUT2 Gamma output pin
9 VDD Logic power supply input
25 OUT1 Gamma output pin
10 SLAVE/AR Slave / Auto-read switching pin
26 OUT0 Gamma output pin
11 SEL REGISTER A/B select pin
27
N.C.
-
12 TEST Pin for test mode
28
VCC
Power supply input
13 DACGND GND input for DAC
29
N.C.
-
14 AGND Buffer AMP GND input
30 REFIN DAC reference voltage input pin
15 OUT11 Gamma output pin
31 VDAC DAC voltage output
16 OUT10 Gamma output pin
32 FB Feedback pin
*In normal use, please connect 12pin TEST pin to OPEN or GND.
www.rohm.com
© 2016 ROHM Co., Ltd. All rights reserved.
5/17
2016.08 - Rev.B
5 Page 
BD8149MUV
Technical Note
(3) In case auto-read starts by VCC power supply input
Auto-read will start at the timing with Under Voltage Lock-Out release.
Gamma output voltage outputs a voltage matching the register setting synchronously after auto-read completion.
SETTING
・ SLAVE/AR = High
・ EN_AR = Low
VDD
VCC
EN_AR
OUT
Hi-z
Auto-read starts
after VCC UVLO release
3 msec(max)
Gamma voltage is outputted
after auto-read completion
Output voltage will be 0V
with UVLO release
*Data reading time by auto-read is 3 msec(max).
*The auto-read starts by the VCC voltage input becomes effective only in the case of 1st auto-read operation after the
VDD voltage input.
< About Data Refresh >
To perform reloading data “Data Refresh”, having EN_AR switches Low to High enables auto-read operation again from
EEPROM, and re-read the data. 10usec holding time is needed to determine EN_AR logic.
Data reading time by auto-read is 3 msec. Should maintain EN_AR=High during that time.
<In case inputting EN_AR=Low during auto-read operation>
If inputting EN_AR=Low during auto-read operation, input from D15 to D0 is completed and write the inputted data to a
register taken back ACK. When EN_AR=Low is determined, the half-way and the following reading data will be invalid.
10usec holding time is needed to determine EN_AR logic.
EN_AR=Low input
EN_AR=Low determination
10 usec
EN AR
DAC(7A) MSbyte. D15-D10 have no meaning
Ackn
DAC(7A) LSbyte
Ackn
DAC(8A) MSbyte. D15-D10 have no meaning
Ackn
DAC(8A) LSbyte
Ackn Stop
SCL
SDA_in D15 D14 D13 D12 D11 D10 D9
D8 Ackn D7 D6
D5 D4 D3 D2 D1 D0 Ackn D15 D14 D13 D12 D11 D10 D9
D8 Ackn D7
D6 D5
D4 D3 D2 D1 D0 Ackn
Device_Out D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1
D0 Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 Ackn
Write data in Register7A
Data is invalid
because of determination EN_AR=Low
Auto-read is ended before taking
back ACK.
www.rohm.com
© 2016 ROHM Co., Ltd. All rights reserved.
11/17
2016.08 - Rev.B
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet BD8149MUV.PDF ] | |
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