PDF XRT91L33A Data sheet ( Hoja de datos )

Número de pieza	XRT91L33A
Descripción	STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
Fabricantes	Exar
Logotipo
Hay una vista previa y un enlace de descarga de XRT91L33A (archivo pdf) en la parte inferior de esta página. Total 18 Páginas
No Preview Available ! XRT91L33A STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT JUNE 2010 REV. 1.0.1 FEATURES  Performs clock and data recovery for selectable data of 622.08 Mbps (STS-12/STM-4) or 155.52 Mbps (STS-3/STM-1) NRZ data  Meets Telcordia, ANSI and ITU-T G.783 and G.825 SDH jitter requirements including T1.105.03 - 2002 SONET Jitter Tolerance specification, and GR-253 CORE, GR-253 ILR SONET Jitter specifications.  LOCK is a status output that monitors data run length and frequency drift away from the reference clock  Data is resampled at the output  Active High Signal Detect (SIGD) LVPECL input  Low jitter, high-speed outputs support LVPECL and low-power LVDS termination  19.44 MHz reference frequency LVTTL input  Low power: 215 mW typical  3.3V power supply  20-pin TSSOP package  Requires one external capacitor  PLL bypass operation facilitates board debug process  ESD greater than 2kV on all pins  Enhanced Jitter performance  Meets both Jitter tolerance and generation requirements APPLICATIONS  SONET/SDH-based Transmission Systems  DSLAMS and Add/Drop Multiplexers  Cross Connect Equipment  ATM and Multi-Service Switches, Routers and Switch/Routers  DWDM Termination Equipment GENERAL DESCRIPTION The XRT91L33A is a fully integrated multirate Clock and Data Recovery (CDR) device for SONET/SDH 622.08 Mbps STS-12/STM-4 or 155.52 Mbps STS-3/ STM-1 applications. The device provides Clock and Data Recovery (CDR) function by synchronizing its on-chip Voltage Controlled Oscillator (VCO) to the incoming serial scrambled non-return to zero (NRZ) data stream. Figure 1 shows the block diagram of the XRT91L33A. FIGURE 1. BLOCK DIAGRAM OF XRT91L33A STS12_MODE REFCK 19.44 MHz CAP+ 1u F CAP- TEST RX LOOP FILTER RXDIP RXDIN External 100R termination Differential Receiver RXDATAIN Internal biasing PLL CDR STS -12/3 or STM-4/1 Clock and Data Recovery LVDS/LVPECL RECVD- Output Drivers DATAOUT 0 1 RECVD- CLKOUT RXDOP RXDON RXCLKOP RXCLKON LCKTOREFN SIGD MUTE RXDO LOCK Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com 1 page REV. 1.0.1 NAME SIGD TEST CAP- CAP+ VSSA VDDA LEVEL LVPECL LVTTL Analog Analog PWR PWR XRT91L33A STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT TYPE I I I I PWR PWR PIN DESCRIPTION 15 Signal detect. SIGD should be connected to the SIGD output on the optical module. SIGD is active HIGH. When SIGD is set HIGH, it means there is sufficient optical power. When SIGD is LOW, this indicates an LOS condition, the RXCLKOP/N output signal will be held to within +/- 500 ppm of the REFCK input. Additionally, the RXDOP/N will be held in the LOW state. 16 Three-level input: Set to VSS for normal operation, VDD for improved Jitter transfer characteristics and 1.4V for bypass mode (used for production testing). Note: To improve Jitter transfer, set the TEST pin to VDD. 17 Negative side of the external loop filter. The loop filter capacitor should be connected to these pins. The capacitor value should be 1.0 F +/- 10% 18 Positive side of the external loop filter. The loop filter capacitor should be connected to these pins. The capacitor value should be 1.0 F +/- 10%. 19 Ground pin 20 3.3V power supply 5 5 Page REV. 1.0.1 XRT91L33A STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT SYMBOL VIH VIL IIH PARAMETER Input HIGH voltage Input LOW voltage Input HIGH current IIL Input LOW current TABLE 9: LVTTL INPUTS MIN. 2.0 TYP. 0 -50 -50 MAX. VDD 0.8 50 50 UNITS V CONDITIONS V A VIN = 2.75 V, VDD = Maximum A VIN = 0.5 V, VDD = Maximum 3.5 AC Characteristics TABLE 10: PERFORMANCE SPECIFICATIONS Test Condition: VDD = 3.3V + 5% unless otherwise specified SYMBOL PARAMETER MIN TYP MAX f VCO center frequency 622.08 fTOL fTREF_CLK CDR’s reference clock frequency OC-12/STS-12 capture range -250 -500 250 500 CLKOUTDC Clock output duty cycle 45 55 tLOCK OC-12/STS-12 acquisition lock time 16 tLOCK_R, tLOCK_F JGEN_CLCK JTOL LOCK output rise and fall time RXCLKOP/N jitter generation OC-12/STS-12 jitter tolerance 500 0.005 0.01 0.40 0.5 UNITS MHz CONDITIONS ppm ppm with respect to the fixed reference frequency % UI 20% minimum transition density s Valid REFCK and device already pow- ered up ps 10% to 90%, with 100  and 5 pF capacitive equivalent load UIrms UI Sinusoidal input jitter of RXDIP/N from 250 KHz to 5MHz 11 11 Page

Páginas	Total 18 Páginas
PDF Descargar	[ Datasheet XRT91L33A.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
XRT91L33	STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT	Exar Corporation
XRT91L33A	STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT	Exar

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar