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PDF XR81112 Data sheet ( Hoja de datos )

Número de pieza XR81112
Descripción LVCMOS/LVDS/LVPECL Clock Synthesizer
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XR81112
Universal Clock - High Frequency
LVCMOS/LVDS/LVPECL Clock Synthesizer
General Description
The XR81112 is a family of Universal Clock synthesizer devices in a com-
pact QFN-12 package. The devices generate ANY frequency in the range of
10 MHz to 1.5GHz by utilizing a highly flexible delta sigma modulator and a
wide ranging VCO. The outputs are configurable for single ended LVCMOS
or differential LVDS or LVPECL. The clock outputs have very low phase
noise jitter of sub 0.6ps while consuming extremely low power. These
devices can be used with standard crystals or an external system clock and
can be configured to select from four different frequency multiplier settings to
support a wide variety of applications. This family of products have an
extremely low power PLL block with core power consumption less than 40%
of equivalent devices in the market.
The XR81112 is a clock synthesizer with Integer/fractional divider, LVCMOS/
LVDS/LVPECL driver, 3.3V/2.5V supply, taking a Xtal input and providing
one of four selectable output frequencies. The device is optimized for use
with a fundamental mode 10MHz to 60MHz crystal (or system clock) and
generates a selection of output frequencies from 10MHz to 1.5GHz in either
integer or fractional mode. In fractional mode, frequency resolution of less
than 1Hz steps can be achieved.
The application diagram below shows a typical synthesizer configuration
with any standard crystal oscillating in fundamental mode. Internal load
capacitors are optionally available to minimize/eliminate external crystal
loads. A system clock can also be used to overdrive the oscillator for a syn-
chronous timing system.
The typical phase noise plot below shows the jitter integrated over the
12KHz to 20MHz range that is widely used in WAN systems. The typical
noise for the integration range of 1.875MHz to 20MHz is sub 200fs which is
important for LAN applications. These clock devices show a very good high
frequency noise floor below -150dB.
FEATURES
• Small footprint 3mm x 3mm QFN package
• Configurable - As one differential LVPECL/LVDS
output pair or as a single ended LVCMOS output
• Crystal oscillator interface which can also be
overdriven using a single-ended reference clock
• Output frequency range: 10MHz - 1500MHz
• Crystal/input frequency: 10MHz to 60MHz, paral-
lel resonant crystal
• VCO range: 2GHz - 3GHz
• RMS phase jitter @ 156.25MHz, 12KHz - 20MHz:
<0.60ps
• Full 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) package
APPLICATIONS
• 10GE, GE LAN/WAN
• 2.5G/10G SONET/SDH/OTN
• xDSL, PCIe
• Low-jitter Clock Generation
• Synchronized clock systems
Ordering Information – back page
Typical Application
XR81112
2.5Vor3.3V
10MHzto60MHz
Enable
FreqSelect
VCC
XTA L _IN
Q
XTA L _OUT
OE
FSEL1
FSEL0
VEE
Q
10MHzto1.5GHz
-40db
-60db
-80db
-100db
-120db
-140db
-160db
-180db
100Hz
XR81112PHASENOISE(dBc/Hz)@156.25MHz
RMS Jitter = 542.0fs
Int Range 12KHz to 20MHz
1KHz
10KHz
100KHz
1MHz
10MHz
© 2014 Exar Corporation
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XR81112 pdf
Pin Configuration
12 11 10
XTAL_IN
1
9 VCC
XTAL_OUT 2
8 VEE
FSEL1
3
7 OE
456
XR81112
Pin Assignments
Pin No.
Pin Name
1 XTAL_IN
2 XTAL_OUT
3 FSEL1
4 FSEL0
5 VEE
6 NC
7 OE
8 VEE
9 VCC
10 Q
11 Q
12 VCC
Type
Description
Input
Crystal oscillator input.
Output
Crystal oscillator output.
Input
Output frequency select pin, MSB (LVCMOS/LVTTL input).
(900K: pull-dwn)
Input
Output frequency select pin, LSB (LVCMOS/LVTTL input).
(900K: pull-dwn)
Supply
Negative supply pin.
No Connect
Input
(900K: pull-up)
Supply
Unused, do not connect.
Output enable pin - LVCMOS/LVTTL active high input. Outputs are enabled when OE = high.
Outputs are disabled when OE = low.
Negative supply pin.
Supply
Power supply pin.
Output
Output
Supply
Positive output.
Inverted output.
Power supply pin.
© 2014 Exar Corporation
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Rev 1A

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XR81112 arduino
Mechanical Dimensions
12-Pin QFN
XR81112
T
T
© 2014 Exar Corporation
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