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PDF GAL22V10 Data sheet ( Hoja de datos )
| Número de pieza | GAL22V10 | |
| Descripción | High Performance E2CMOS PLD Generic Array Logic | |
| Fabricantes | Lattice Semiconductor | |
| Logotipo |  |
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GAL22V10LePAOaavpdact-kiliFaaorgbneelsee!
Specifications GAL22V10
High Performance E2CMOS PLD
Generic Array Logic™
Features
Functional Block Diagram
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 4 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 3.5 ns Maximum from Clock Input to Data Output
— UltraMOS® Advanced CMOS Technology
• ACTIVE PULL-UPS ON ALL PINS
• COMPATIBLE WITH STANDARD 22V10 DEVICES
— Fully Function/Fuse-Map/Parametric Compatible
with Bipolar and UVCMOS 22V10 Devices
• 50% to 75% REDUCTION IN POWER VERSUS BIPOLAR
— 90mA Typical Icc on Low Power Device
— 45mA Typical Icc on Quarter Power Device
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• TEN OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
• PRELOAD AND POWER-ON RESET OF REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
• LEAD-FREE PACKAGE OPTIONS
ESCRIPTION
Description
The GAL22V10, at 4ns maximum propagation delay time, combines
a high performance CMOS process with Electrically Erasable (E2)
floating gate technology to provide the highest performance avail-
able of any 22V10 device on the market. CMOS circuitry allows
the GAL22V10 to consume much less power when compared to
bipolar 22V10 devices. E2 technology offers high speed (<100ms)
erase times, providing the ability to reprogram or reconfigure the
device quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL22V10 is fully function/fuse map/parametric com-
patible with standard bipolar and CMOS 22V10 devices.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lat-
tice Semiconductor delivers 100% field programmability and func-
tionality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
I/CLK
I
I
I
I
I
I
I
I
I
I
I
Pin Configuration
PLCC
4
I5
2 28 26
25 I/O/Q
I I/O/Q
I7
NC
I9
GAL22V10 23 I/O/Q
Top View
NC
21 I/O/Q
I I/O/Q
I 11
19 I/O/Q
12 14 16 18
SOIC
GAL22V10
Top View
RESET
8
OLMC
10
OLMC
12
OLMC
14
OLMC
16
OLMC
16
OLMC
14
OLMC
12
OLMC
10
OLMC
8
OLMC
PRESET
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
DIP
I/CLK
I
I
I
I
I
I
I
I
I
I
GND
1 24
GAL
22V10
6
18
12 13
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
December 2006
22v10_12
1
1 page  
Registered Mode
AR
DQ
CLK
Q
SP
S0 = 0
S1 = 0
ACTIVE LOW
Combinatorial Mode
Specifications GAL22V10
AR
DQ
CLK
Q
SP
S0 = 1
S1 = 0
ACTIVE HIGH
S0 = 0
S1 = 1
ACTIVE LOW
S0 = 1
S1 = 1
ACTIVE HIGH
5
5 Page 
fmax Descriptions
CLK
LOGIC
ARRAY
REGISTER
tsu tco
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is cal-
culated from measured tsu and tco.
CLK
LOGIC
ARRAY
REGISTER
tsu + th
fmax with No Feedback
Note: fmax with no feedback may be less
than 1/(twh + twl). This is to allow for a
clock duty cycle of other than 50%.
Specifications GAL22V10
LOGIC
ARRAY
CLK
REGISTER
t cf
t pd
fmax with Internal Feedback 1/(tsu+tcf)
Note: tcf is a calculated value, derived by sub-
tracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combi-
natorial output is equal to tcf + tpd.
11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet GAL22V10.PDF ] | |
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