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PDF FDMC2514SDC Data sheet ( Hoja de datos )
| Número de pieza | FDMC2514SDC | |
| Descripción | N-Channel Dual Cool PowerTrench SyncFET | |
| Fabricantes | Fairchild Semiconductor | |
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FDMC2514SDC
N-Channel Dual CoolTM PowerTrench® SyncFETTM
25 V, 40 A, 3.5 mΩ
October 2010
Features
Dual CoolTM Top Side Cooling PQFN package
Max rDS(on) = 3.5 mΩ at VGS = 10 V, ID = 22.5 A
Max rDS(on) = 4.7 mΩ at VGS = 4.5 V, ID = 18 A
High performance technology for extremely low rDS(on)
SyncFET Schottky Body Diode
RoHS Compliant
General Description
This N-Channel MOSFET is produced using Fairchild
Semiconductor’s advanced PowerTrench® process.
Advancements in both silicon and Dual CoolTM package
technologies have been combined to offer the lowest rDS(on)
while maintaining excellent switching performance by extremely
low Junction-to-Ambient thermal resistance. This device has the
added benefit of an efficient monolithic Schottky body diode.
Applications
Synchronous Rectifier for DC/DC Converters
Telecom Secondary Side Rectification
High End Server/Workstation Vcore Low Side
Pin 1
G
S
S
S
D5
4G
D6
3S
D
D
D
D
Top Power 33
Bottom
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Symbol
VDS
VGS
ID
EAS
dv/dt
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous (Package limited)
-Continuous (Silicon limited)
-Continuous
-Pulsed
TC = 25 °C
TC = 25 °C
TA = 25 °C
Single Pulse Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation
TC = 25 °C
Power Dissipation
TA = 25 °C
Operating and Storage Junction Temperature Range
Thermal Characteristics
D7
D8
(Note 4)
(Note 1a)
(Note 3)
(Note 5)
(Note 1a)
2S
1S
Ratings
25
±20
40
106
24
200
84
2.0
60
3.0
-55 to +150
Units
V
V
A
mJ
V/ns
W
°C
RθJC
RθJC
RθJA
RθJA
RθJA
RθJA
RθJA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Package Marking and Ordering Information
(Top Source)
(Bottom Drain)
(Note 1a)
(Note 1b)
(Note 1i)
(Note 1j)
(Note 1k)
5.8
2.1
42
105
17
26
12
°C/W
Device Marking
2514S
Device
FDMC2514SDC
©2010 Fairchild Semiconductor Corporation
FDMC2514SDC Rev.C2
Package
Dual CoolTM Power 33
1
Reel Size
13’’
Tape Width
12 mm
Quantity
3000 units
www.fairchildsemi.com
1 page  
Typical Characteristics TJ = 25 °C unless otherwise noted
10
ID = 22.5 A
8
6
4
VDD = 10 V
VDD = 16 V
VDD = 13 V
3000
1000
Ciss
Coss
2
0
0 4 8 12 16 20 24 28 32
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
30
TJ = 25 oC
10
TJ = 100 oC
TJ = 125 oC
100 f = 1 MHz
VGS = 0 V
60
0.1
1
Crss
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
Figure8. CapacitancevsDrain
to Source Voltage
120
VGS = 10 V
RθJC = 2.1 oC/W
80
VGS = 4.5 V
40
1
0.01
0.1 1 10
tAV, TIME IN AVALANCHE (ms)
Figure9. UnclampedInductive
Switching Capability
100
300
100
100 us
10 1ms
THIS AREA IS
1 LIMITED BY rDS(on)
SINGLE PULSE
0.1
TJ = MAX RATED
RθJA = 105 oC/W
TA = 25 oC
0.01
0.01 0.1 1 10
VDS, DRAIN to SOURCE VOLTAGE (V)
10 ms
100 ms
1s
10 s
DC
100
Figure 11. Forward Bias Safe
Operating Area
Limited by Package
0
25 50 75 100 125
TC, CASE TEMPERATURE (oC)
Figure 10. Maximum Continuous Drain
Current vs Case Temperature
150
2000
1000
100
SINGLE PULSE
RθJA = 105 oC/W
TA = 25 oC
10
1
0.5
10-4 10-3 10-2 10-1
1
10
t, PULSE WIDTH (sec)
100 1000
Figure 12. Single Pulse Maximum
Power Dissipation
©2010 Fairchild Semiconductor Corporation
FDMC2514SDC Rev.C2
5
www.fairchildsemi.com
5 Page | ||
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| PDF Descargar | [ Datasheet FDMC2514SDC.PDF ] | |
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