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PDF LC717A10AJ Data sheet ( Hoja de datos )
| Número de pieza | LC717A10AJ | |
| Descripción | Capacitance-Digital-Converter LSI | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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Ordering number : ENA2162
LC717A10AJ
CMOS LSI
Capacitance-Digital-Converter LSI
for Electrostatic Capacitive Touch
Sensors
http://onsemi.com
Overview
The LC717A10AJ is a high-performance and low-cost capacitance-digital-converter LSI for electrostatic capacitive
touch sensor, especially focused on usability.
It has 16 channels capacitance-sensor input. This makes it ideal for use in the products that need many switches.
Since the calibration function and the judgment of ON/OFF are automatically performed in LSI internal, it can make
development time more short. A detection result (ON/OFF) for each input can be read out by the serial interface (I2C
compatible bus or SPI).
Also, measurement value of each input can be read out as 8-bit digital data. Moreover, gain and other parameters can
be adjusted using serial interface.
Features
• Detection system: Differential capacitance detection (Mutual capacitance type)
• Input capacitance resolution: Can detect capacitance changes in the femto Farad order
• Measurement interval (16 differential inputs): 30ms (Typ) (at initial configuration),
6ms (Typ) (at minimum interval configuration)
• External components for measurement: Not required
• Interface: I2C * compatible bus or SPI selectable.
• Current consumption: 570μA (Typ) (VDD = 2.8V), 1.3mA (Typ) (VDD = 5.5V)
• Supply voltage: 2.6V to 5.5V
• Detection operations: Switch
• Packages: SSOP30
* I2C Bus is a trademark of Philips Corporation.
Semiconductor Components Industries, LLC, 2013
August, 2013
Ver1.0.1
D1912HKPC 20121204-S00003 No.A2162-1/11
1 page  
LC717A10AJ
Power-on Reset (POR)
When power is turned on, power-on reset is enabled inside the LSI and its state is released after a certain power-on reset
time, tPOR. Power-on Reset operation condition; Power supply rise rate tVDD must be at least 1V/ms.
Since INTOUT pin changes from “High” to “Low” at the same time as the released of power-on reset, it is possible to
verify the timing of release of power-on reset externally.
During power-on reset, Cin, Cref and CrefAdd are unknown.
VDD
tVDD
tPOR
POR
(LSI internal signal)
RESET
RELEASE
VPOROP
tPOROP
tPOR
UNKNOWN RESET
RELEASE
INTOUT
VALID UNKNOWN
Cin,
Cref,
CrefAdd
UNKNOWN
VALID
UNKNOWN
I2C Compatible Bus Data Timing
fig.1
SDA
10%
90%
10%
SCL
tLOW
tHD;DTA tSU;DTA
90% 90%
90%
10% 10%
10%
tHIGH
10%
tHD;STA
tr tf
START
condition
tSU;STA
90%
90%
10%
tHD;STA
90%
repeated START
condition
fig.2
90%
10%
tSU;STO
tBUF
90%
10%
90%
STOP
condition
START
condition
I2C Compatible Bus Communication Formats
• Write format (data can be written into sequentially incremented addresses)
START
Slave Address
Write=L ACK
Slave
Register Address (N)
ACK Data written to Register Address (N) ACK Data written to Register Address (N+1) ACK STOP
Slave
fig.3
Slave
Slave
• Read format (data can be read from sequentially incremented addresses)
START
Slave Address
RESTART
Slave Address
Write=L ACK
Slave
Register Address (N)
ACK
Slave
Read=H ACK Data read from Register Address (N) ACK Data read from Register Address (N+1) ACK Data read from Register Address (N+2) NACK STOP
Slave
Master
fig.4
Master
Master
No.A2162-5/11
5 Page 
LC717A10AJ
●nCS
Interface selection / Chip-select-inverting input (SPI)
Selection of I2C compatible bus mode or SPI mode is through this terminal. After initialization, the LSI is
automatically in I2C compatible bus mode. To continually use I2C compatible bus mode, fix nCS pin to “High”. To
switch to SPI mode after LSI initialization, change the nCS input “High” → “Low”. The nCS pin is used as the chip-
select-inverting input pin of SPI, and SPI mode is kept until LSI is again initialized.
●nRST
It is the external-reset-signal-inverting-input pin. When nRST pin is “Low”, LSI is in reset state.
Each pin (Cin0 to 15, Cref, CrefAdd) is “Hi-Z” during reset state.
●SDA/SI
Data input and output (I2C) / Data input (SPI)
It is the data input and output pin of the I2C compatible bus or the data input pin of the SPI depending on the mode of
operation.
●SA0/SO
Slave address selection (I2C) / Data output (SPI)
It is the slave address selection pin of the I2C compatible bus or the data output pin of the SPI depending on the mode
of operation.
●SA1
Slave address selection (I2C)
It is the slave address selection pin of the I2C compatible bus.
When SPI mode, connect to the SA1 pin to GND.
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number
of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at
www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no
warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the
application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use
as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in
which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for
any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or
death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the
part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PS No.A2162-11/11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet LC717A10AJ.PDF ] | |
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