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PDF ADT7476 Data sheet ( Hoja de datos )
| Número de pieza | ADT7476 | |
| Descripción | Remote Thermal Controller and Voltage Monitor | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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ADT7476
Remote Thermal Controller
and Voltage Monitor
The ADT7476 controller is a thermal monitor and multiple PWM
fan controller for noise-sensitive or power-sensitive applications
requiring active system cooling. The ADT7476 can drive a fan using
either a low or high frequency drive signal and can monitor the
temperature of up to two remote sensor diodes plus its own internal
temperature. The part also measures and controls the speed of up to
four fans, so the fans operate at the lowest possible speed for minimum
acoustic noise.
The automatic fan speed control loop optimizes fan speed
for a given temperature. The effectiveness of the system’s thermal
solution can be monitored using the THERM input. The ADT7476
also provides critical thermal protection to the system using the
bidirectional THERM pin as an output to prevent system or
component overheating.
Features
• Monitors Up to Five Voltages
• Controls and Monitors Up to Four Fans
• High and Low Frequency Fan Drive Signal
• One On-Chip and Two Remote Temperature Sensors
• Extended Temperature Measurement Range Up to 191°C
• Automatic Fan Speed Control Mode Controls System Cooling Based
on Measured Temperature
• Enhanced Acoustic Mode Dramatically Reduces User Perception of
Changing Fan Speeds
• Thermal Protection Feature via THERM Output
• Monitors Performance Impact of Intel® Pentium® 4 Processor
• Thermal Control Circuit via THERM Input
• 3-wire and 4-wire Fan Speed Measurement
• Limit Comparison of All Monitored Values
• Meets SMBus 2.0 Electrical Specifications
• This Device is Pb-Free, Halogen Free and is RoHS Compliant
www.onsemi.com
QSOP−24 NB
CASE 492B
PIN ASSIGNMENT
SDA 1
24 PWM1/XTO
SCL 2
23 VCCP
GND 3
22 +2.5VIN/THERM
VCC 4
21 +12VIN/VID5
VID0/GPIO0 5
20 +5VIN
VID1/GPIO1 6
19 VID4/GPIO4
ADT7476
VID2/GPIO2 7 (Top View) 18 D1+
VID3/GPIO3 8
17 D1−
TACH3
PWM2/
SMBALERT
TACH1
9
10
11
16 D2+
15 D2−
14 *
TACH2 12
13 PWM3/ADDREN
*TACH4/THERM/SMBALERT/GPIO6/ADDR SELECT
MARKING DIAGRAMS
ADT7476RQZ
#YYWW
xxxx
ADT7476RQZ
#
YYWW
xxxx
= Specific Device Code
= Pb-Free Package
= Date Code
= Assembly Lot Code
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 67 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
February, 2016 − Rev. 10
1
Publication Order Number:
ADT7476/D
1 page  
ADT7476
Table 4. ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.) (Note 1)
Parameter
Conditions
Min Typ Max Unit
Digital Input Logic Levels (THERM) ADTL+
Input High Voltage, VIH
Input Low Voltage, VIL
Digital Input Current
Input High Current, IIH
Input Low Current, IIL
Input Capacitance, CIN
Serial Bus Timing (See Figure 2)
VIN = VCC
VIN = 0 V
0.75 x VCCP
−
−
−
−V
0.8 V
− ±1 − mA
− ±1 − mA
− 5.0 − pF
Clock Frequency, fSCLK
10 − 400 kHz
Glitch Immunity, tSW
− − 50 ns
Bus Free Time, tBUF
4.7 −
− ms
SCL Low Time, tLOW
4.7 −
− ms
SCL High Time, tHIGH
4.0 − 50 ms
SCL, SDA Rise Time, tr
−
−
1,000
ns
SCL, SDA Fall Time, tf
− − 300 ms
Data Setup Time, tSU;DAT
250 −
− ns
Detect Clock Low Timeout, tTIMEOUT
Can be Optionally Disabled
15 − 35 ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. All voltages are measured with respect to GND, unless otherwise specified. Typical voltages are TA = 25°C and represent a parametric norm.
Logic inputs accept input high voltages up to VMAX, even when the device is operating down to VMIN. Timing specifications are tested at logic
levels of VIL = 0.8 V for a falling edge, and VIH = 2.0 V for a rising edge.
2. SMBus timing specifications are guaranteed by design and are not production tested.
SCL
SDA
tBUF
PS
t LOW
tR
tHD; STA
tHD; DAT
tF
tHIGH
tSU; DAT
t HD; STA
tSU; STA
S
Figure 2. Serial Bus Timing Diagram
tSU; STO
P
www.onsemi.com
5
5 Page 
ADT7476
1
SCL
91
9
SDA
0
START BY
MASTER
1 0 1 1 A1 A0
FRAME 1
SERIAL BUS ADDRESS BYTE
R/W D7
ACK. BY
ADT7476
D6 D5 D4 D3 D2 D1 D0
NO ACK. BY
FRAME 2
MASTER
DATA BYTE FROM ADT7476
STOP BY
MASTER
Figure 20. Reading Data from a Previously Selected Register
Write Operations
The SMBus specification defines several protocols for
different types of read and write operations. The ones used
in the ADT7476 are discussed below. The following
abbreviations are used in the diagrams:
• S – START
• P – STOP
• R – READ
• W– WRITE
• A – ACKNOWLEDGE
• A – NO ACKNOWLEDGE
The ADT7476 uses the following SMBus write protocols.
Send Byte
In this operation, the master device sends a single
command byte to a slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA, and
the transaction ends.
For the ADT7476, the send byte protocol is used to write
a register address to RAM for a subsequent single-byte read
from the same address. This operation is illustrated in
Figure 21.
12
3 4 56
S
SLAVE
ADDRESS
W
A
REGISTER
ADDRESS
AP
Figure 21. Setting a Register Address for
Subsequent Read
If the master is required to read data from the register
immediately after setting up the address, it can assert a repeat
start condition immediately after the final ACK and carry
out a single byte read without asserting an intermediate stop
condition.
Write Byte
In this operation, the master device sends a command byte
and one data byte to the slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master asserts a stop condition on SDA,
and the transaction ends.
This operation is illustrated in Figure 22.
12
3 4 5 6 78
S
SLAVE
ADDRESS
W
A
REGISTER
ADDRESS
A DATA
AP
Figure 22. Single-byte Write to a Register
Read Operations
The ADT7476 uses the following SMBus read protocols.
Receive Byte
This operation is useful when repeatedly reading a single
register. The register address is set up beforehand. In this
operation, the master device receives a single byte from a
slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed
by the read bit (high).
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
5. The master asserts NO ACK on SDA.
6. The master asserts a stop condition on SDA, and
the transaction ends.
In the ADT7476, the receive byte protocol is used to read
a single byte of data from a register whose address has
previously been set by a send byte or write byte operation.
This operation is illustrated in Figure 23.
12
34
S
SLAVE
ADDRESS
R
A
DATA
56
AP
Figure 23. Single-byte Read from a Register
Alert Response Address
Alert response address (ARA) is a feature of SMBus
devices, allowing an interrupting device to identify itself to
the host when multiple devices exist on the same bus.
The SMBALERT output can be used as either an interrupt
output or an SMBALERT. One or more outputs can be
connected to a common SMBALERT line connected to the
www.onsemi.com
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADT7476.PDF ] | |
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