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PDF KAI-1003 Data sheet ( Hoja de datos )
| Número de pieza | KAI-1003 | |
| Descripción | Interline CCD Image Sensor | |
| Fabricantes | ON Semiconductor | |
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KAI-1003
1024 (H) x 1024 (V) Interline
CCD Image Sensor
Description
The KAI−1003 Image Sensor is a high-performance megapixel
monochrome image sensor designed for a wide range of medical
imaging and machine vision applications.
The 12.8 mm square pixels with microlenses provide high sensitivity
and the large capacity results in large dynamic range. The two output,
split horizontal register and several binning modes allow a 15 to 60
frame per second (fps) video rate for the progressively scanned
images.
The vertical overflow drain structure provides anti-blooming
protection, and enables electronic shuttering for precise exposure
control. Other features include low dark current, negligible lag and
low smear.
Table 1. GENERAL SPECIFICATIONS
Parameter
Typical Value
Architecture
Interline CDD; Progressive Scan
Total Number of Pixels
1056 (H) × 1032 (V)
Number of Effective Pixels
1028 (H) × 1028 (V)
Number of Active Pixels
1024 (H) × 1024 (V)
Pixel Size
12.8 mm(H) × 12.8 mm (V)
Active Image Size
13.1 mm (H) × 13.1 mm (V),
18.5 mm (Diagonal),
4/3″ Optical Format
Aspect Ratio
1:1
Number of Outputs
Charge Capacity
Output Sensitivity
1 or 2
170,000 e−
7.5 mV/e−
Quantum Efficiency (500 nm)
Read Noise (f = 20 MHz)
Dark Current
45%
40 e− rms
< 0.5 nA/cm2
Dynamic Range
72 dB
Blooming Suppression
> 100 X
Smear
−80 dB
Maximum Pixel Clock Speed
20 MHz
Maximum Frame Rate
Single Output
Dual Output
Dual Output 2×2 Bin
15 fps
30 fps
60 fps
Package
28-Pin CERDIP
Cover Glass
AR Coated, 2 Sides
NOTE: All Parameters are specified at T = 40°C unless otherwise noted.
www.onsemi.com
Figure 1. KAI−1003 Interline
CCD Image Sensor
Features
• Megapixel Progressive Scan Interline CCD
• 1024 (H) × 1024 (V) Imaging Pixels
• 12.8 mm Square Pixels
• 13.1 mm Square Imaging Area
• Microlenses for Increased Sensitivity
• Large Capacity (170 ke−)
• Split Horizontal Register for 1 or 2 Outputs
• Binning to 1 × 2 or 2 × 2
Applications
• Machine Vision
• Medical
• Scientific
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2015
November, 2015 − Rev. 2
1
Publication Order Number:
KAI−1003/D
1 page  
KAI−1003
Output Structure
Charge presented to the floating diffusion (FD) is
converted into a voltage and current amplified in order to
drive off-chip loads. The resulting voltage change seen at the
output is linearly related to the amount of charge placed on
the FD. Once the signal has been sampled by the system
electronics, the reset gate (fR) is clocked to remove the
signal and the FD is reset to the potential applied by the reset
drain (RD). More signal at the floating diffusion reduces the
voltage seen at the output pin. In order to activate the output
structure, an off-chip load must be added to the output pin
of the device.
Non-Imaging Pixels
In addition to the 1024 (H) by 1024 (V) imaging pixels,
there are active buffer, light shielded and empty pixels, as
shown in Figure 2. A two-pixel border of active buffer pixels
surrounds the imaging area. These buffer pixels respond to
illumination but are not tested for defects and
non-uniformities. Two light shielded rows lead and follow
each frame, and 14 light shielded columns lead and follow
each line. The light shielded columns are tested for column
defects and can be used for dark reference. Only the center
10 columns by 1028 rows of light shielded region on each
side can be used for dark reference due to light leakage into
the border of two pixels at the edges. Finally, two empty
pixels occur at the beginning of each line, which are empty
shift register cycles not associated with any vertical CCD
columns. Empty pixels may also occur at the end of the line,
depending on the timing.
In-Phase
H1A = H1B = H1C
H2A = H2B = H2C
Dual Outputs
Out-of-Phase
H1A − 1/2 = H1B = H1C
H2A − 1/2 = H2B = H2C
Single Output
H1A = H1B = H2C
H2A = H2B = H1C
Figure 3. Horizontal CCD Registers
www.onsemi.com
5
5 Page 
KAI−1003
Table 10. AC CLOCK LEVEL CONDITIONS
Description
Level
Symbol
Min.
Nom.
Max.
Unit
Vertical CCD Clocks
(Note 1)
High
Mid
fV2H
9.5 10.5 11.5
fV1M, fV2M
−0.8
−0.5
0.0
V
V
Low
fV1L, fV2L
−9.0
−8.5
−8.0
V
Horizontal CCD Clocks
(Note 1)
High
Low
fH1H, fH2H
4.5
5.0
5.5
fH1L, fH2L
−6.5
−6.0
−5.5
V
V
Reset Clock
Amplitude
fRSWING
−
5.0
−
V
Low (Note 2)
VfRlow
0 TBS 5.0
V
Electronic Shutter Pulse (Notes 3, 4)
Shutter
VSHUTTER
37
40
45
V
1. For best results, the CCD clock swings must be greater than or equal to the nominal values.
2. Reset clock low level voltage will be supplied with each shipment.
3. Electronic shutter pulse voltage referenced to GND. See DC Operating Conditions for DC level when electronic shutter is not in use.
4. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
Electronic Shutter Operation
Electronic shuttering is accomplished by pulsing the
substrate voltage to empty the photodiodes. See Figure 16
Table 11. CALCULATED CLOCK CAPACITANCE
Description
Phase
Vertical CCD Clocks
(Note 1)
1 to GND
2 to GND
1 to 2
Horizontal CCD Clocks
(Notes 1, 2)
1A
1B
1C
2A
2B
2C
HCCD Summing Clock
Reset Clock − GND
1. Accumulation/depletion capacitances.
2. Capacitance of this gate to GND and all other gates.
for timing. The pulse must not occur while useful
information is being read from a line.
Symbol
C fV1
C fV2
C fV1 − fV2
C fH1A
C fH1B
C fH1C
C fH2A
C fH2B
C fH2C
C fH22A/B
C fRA/B
Typical
55/37
50/32
4
58/21
41/13
15/10
48/22
30/11
18/13
3
5
Unit
nF
nF
nF
pF
pF
pF
pF
pF
pF
pF
pF
www.onsemi.com
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