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Número de pieza | DP7261 | |
Descripción | Dual Digital Potentiometers | |
Fabricantes | COPAL ELECTRONICS | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de DP7261 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
No Preview Available ! Dual Digital Potentiometers
(DP) with 256 Taps and SPI Interface
DP7261
FEATURES
Two linear-taper digital potentiometers
256 resistor taps per potentiometer
End to end resistance 50k or 100k
Potentiometer control and memory access via
SPI interface
Low wiper resistance, typically 100
Nonvolatile memory storage for up to four
wiper settings for each potentiometer
Automatic recall of saved wiper settings at
power up
2.5 to 6.0 volt operation
Standby current less than 1µA
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
24-lead SOIC and 24-lead TSSOP
Industrial temperature range
Industrial temperature range
For Ordering Information details, see page 14.
DESCRIPTION
The DP7261 is two Digital Potentiometers
(DPs) integrated with control logic and 8 bytes of
NVRAM memory. Each DP consists of a series
of resistive elements connected between two
externally accessible end points. The tap points
between each resistive element are connected to the
wiper outputs with CMOS switches. A separate 8-bit
control register (WCR) independently controls the wiper
tap switches for each DP. Associated with each wiper
control register are four 8-bit non-volatile memory data
registers (DR) used for storing up to four wiper settings.
Writing to the wiper control register or any of the non-
volatile data registers is via a SPI serial bus. On power-
up, the contents of the first data register (DR0) for each
of the potentiometers is automatically loaded into its
respective wiper control register.
The DP7261 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications. It is available in the -40°C to 85°C
industrial operating temperature range and offered in
a 24-lead SOIC and TSSOP package.
PIN CONFIGURATION
SOIC/TSSOP (W, Y)
SO 1
24 H¯¯O¯L¯D¯
A0 2
23 SCK
NC 3
22 NC
NC 4
21 NC
NC 5
20 NC
NC
6
DP
7261
19
NC
VCC 7
18 GND
RL0 8
17 RW1
RH0 9
16 RH1
RW0 10
¯C¯S¯ 11
15 RL1
14 A1
¯W¯P¯ 12
13 SI
FUNCTIONAL DIAGRAM
CS
SCK
SI
SO
SPI BUS
INTERFACE
WIPER
CONTROL
REGISTERS
RH0 RH1
WP
A0
A1
HOLD
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
RL0 RL1
RW0
RW1
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
1
Doc. No. MD-2122 Rev. D
1 page DP7261
D.C. OPERATING CHARACTERISTICS
VCC = +2.5V to +6.0V, unless otherwise specified.
Symbol Parameter
Test Conditions
Min
ICC1 Power Supply Current
fSCL = 400kHz, SDA = Open
VCC = 6V, Inputs = GNDs
Power Supply Current
ICC2 Non-volatile WRITE
fSCK = 400kHz, SDA Open
VCC = 6V, Input = GND
ISB Standby Current (VCC = 5.0V) VIN = GND or VCC, SDA = Open
ILI Input Leakage Current
VIN = GND to VCC
ILO Output Leakage Current
VOUT = GND to VCC
VIL Input Low Voltage
-1
VIH Input High Voltage
VCC x 0.7
VOL1 Output Low Voltage (VCC = 3.0V) IOL = 3mA
VOH1 Output High Voltage
IOH = -1.6mA
VCC – 0.8
PIN CAPACITANCE(1)
TA = 25ºC, f = 1.0MHz, VCC = 5V, unless otherwise specified.
Symbol
COUT(1)
CIN(1)
Test
Output Capacitance (SO)
Input Capacitance (¯C¯S¯, SCK, SI, ¯W¯P¯,H¯¯O¯L¯D¯, A0, A1)
Conditions
VOUT = 0V
VIN = 0V
A.C. CHARACTERISTICS
Symbol Parameter
Test Conditions
Min
tSU Data Setup Time
tH Data Hold Time
tWH SCK High Time
tWL SCK Low Time
fSCK Clock Frequency
tLZ H¯¯O¯L¯D¯ to Output Low Z
tRI(1) Input Rise Time
tFI(1) Input Fall Time
tHD H¯¯O¯L¯D¯ Setup Time
tCD H¯¯O¯L¯D¯ Hold Time
tV Output Valid from Clock Low
tHO Output Hold Time
tDIS Output Disable Time
tHZ H¯¯O¯L¯D¯ to Output High Z
tCS ¯C¯S¯ High Time
tCSS ¯C¯S¯ Setup Time
tCSH ¯C¯S¯ Hold Time
CL = 50pF
50
50
125
125
DC
100
100
0
2
250
250
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Max
1
5
1
10
10
VCC x 0.3
VCC + 1.0
0.4
Max
8
6
Max
3
50
2
2
200
250
100
Units
mA
mA
µA
µA
µA
V
V
V
V
Units
pF
pF
Units
ns
ns
ns
ns
MHz
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
5
Doc. No. MD-2122 Rev. E
5 Page Global Transfer Data Register (DR) to Wiper Control Register (WCR)
DEVICE ADDRESSES
INSTRUCTION
¯C¯S¯ 0 1 0 1 0 0 A A 0 0 0 1 R R 0 0 ¯C¯S¯
10
10
DP7261
Global Transfer Wiper Control Register (WCR) to Data Register (DR)
DEVICE ADDRESSES
INSTRUCTION
¯C¯S¯ 0 1 0 1
0
0
A
1
A
0
1 0 0 0RR
10
0
0
¯C¯S¯
High Voltage
Write Cycle
Transfer Wiper Control Register (WCR) to Data Register (DR)
DEVICE ADDRESSES
INSTRUCTION
¯C¯S¯ 0 1 0 1 0
0
A
1
A
0
1110RR
10
P
1
P
0
¯C¯S¯
High Voltage
Write Cycle
Transfer Data Register (DR) to Wiper Control Register (WCR)
DEVICE ADDRESSES
INSTRUCTION
¯C¯S¯ 0 1 0 1 0 0 A A 1 1 0 1 R R P P ¯C¯S¯
10
10 1 0
Increment (I)/Decrement (D) Wiper Control Register (WCR)
DEVICE ADDRESSES
INSTRUCTION
¯C¯S¯ 0 1 0 1 0 0 A A 0 0 1 0 0 0 P P I/D I/D
10
10
DATA
...
I/D I/D ¯C¯S¯
Notes:
(1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued.
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
11
Doc. No. MD-2122 Rev. E
11 Page |
Páginas | Total 15 Páginas | |
PDF Descargar | [ Datasheet DP7261.PDF ] |
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