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PDF 74ALVCH16245 Data sheet ( Hoja de datos )
| Número de pieza | 74ALVCH16245 | |
| Descripción | LOW VOLTAGE CMOS 16-BIT TRANSCEIVER | |
| Fabricantes | STMicroelectronics | |
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74ALVCH16245
LOW VOLTAGE CMOS 16-BIT TRANSCEIVER (3-STATE)
WITH 3.6V TOLERANT INPUTS AND OUTPUTS
s 3.6V TOLERANT INPUTS AND OUTPUTS
s HIGH SPEED:
tPD = 3.0 ns (MAX.) at VCC = 3.0 to 3.6V
tPD = 3.7 ns (MAX.) at VCC = 2.3 to 2.7V
tPD =6 ns (MAX.) at VCC = 1.65V
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) at VCC = 3.0V
|IOH| = IOL = 12mA (MIN) at VCC = 2.3V
|IOH| = IOL = 4mA (MIN) at VCC = 1.65V
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 1.65V to 3.6V
s BUS HOLD PROVIDED ON DATA INPUTS
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16245
s LATCH-UP PERFORMANCE EXCEEDS
300mA (JESD 17)
s ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74ALVCH16245 is a low voltage CMOS 16
BIT BUS TRANSCEIVER fabricated with
sub-micron silicon gate and five-layer metal wiring
C2MOS technology. It is ideal for low power and
very high speed 1.65 to 3.6V applications; it can
be interfaced to 3.6V signal environment for both
inputs and outputs.
This IC is intended for two-way asynchronous
communication between data busses; the
direction of data transmission is determined by
DIR input. The enable input G can be used to
disable the device so that the busses are
effectively isolated.
Bus hold on data inputs is provided in order to
eliminate the need for external pull-up or
pull-down resistor.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
TSSOP
ORDER CODES
PACKAGE
TSSOP
TUBE
PIN CONNECTION
T&R
74ALVCH16245TTR
July 2003
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1 page  
74ALVCH16245
AC ELECTRICAL CHARACTERISTICS
Test Condition
Value
Symbol
Parameter
VCC
CL RL ts = tr -40 to 85 °C
-55 to 125 °C Unit
(V) (pF) (Ω) (ns) Min. Max. Min. Max.
tPLH tPHL Propagation Delay 1.65 to 1.95 30 1000 2.0
1
6
1
6
Time
2.3 to 2.7 30 500 2.0
1
3.7
1
3.7
2.7
50 500 2.5
1
3.6
1
3.6
3.0 to 3.6 50 500 2.5
1
3.0
1
3.0
tPZL tPZH Output Enable Time 1.65 to 1.95 30 1000 2.0
1
7.1
1
7.1
2.3 to 2.7 30 500 2.0
1
5.7
1
5.7
ns
2.7
50 500 2.5
1
5.4
1
5.4
3.0 to 3.6 50 500 2.5
1
4.4
1
4.4
tPLZ tPHZ Output Disable Time 1.65 to 1.95 30 1000 2.0
1
7.0
1
7.0
2.3 to 2.7 30 500 2.0
1
5.2
1
5.2
2.7
50 500 2.5
1
4.6
1
4.6
3.0 to 3.6 50 500 2.5
1
4.1
1
4.1
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|)
2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS
Test Condition
Value
Symbol
Parameter
VCC
(V)
TA = 25 °C
Min. Typ. Max.
Unit
CIN Input Capacitance Control
Inputs
3.3 VIN =VCC or GND
4
pF
CI/O Input Capacitance A or B ports
3.3
VIN =VCC or GND
8
pF
CPD Power Dissipation Capacitance
Output enabled (note 1)
CPD Power Dissipation Capacitance
Output disabled (note 1)
3.3
2.5
3.3
2.5
fIN = 10MHz
CL=50pF
VIN = 0 or VCC
29
22
pF
5
4
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/16 (per
circuit)
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74ALVCH16245.PDF ] | |
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