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PDF AD5451 Data sheet ( Hoja de datos )
| Número de pieza | AD5451 | |
| Descripción | 8-/10-/12-/14-Bit High Bandwidth Multiplying DACs | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
8-/10-/12-/14-Bit High Bandwidth
Multiplying DACs with Serial Interface
AD5450/AD5451/AD5452/AD5453
FEATURES
12 MHz multiplying bandwidth
INL of ±0.25 LSB at 8-bit
8-lead TSOT and MSOP packages
2.5 V to 5.5 V supply operation
Pin-compatible 8-/10-/12-/14-bit current output DACs
±10 V reference input
50 MHz serial interface
2.7 MSPS update rate
Extended temperature range: –40°C to +125°C
4-quadrant multiplication
Power-on reset with brownout detect
<0.4 µA typical current consumption
Guaranteed monotonic
Qualified for automotive applications
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
GENERAL DESCRIPTION
The AD5450/AD5451/AD5452/AD54531 are CMOS 8-/10-/12-/
14-bit current output digital-to-analog converters, respectively.
These devices operate from a 2.5 V to 5.5 V power supply,
making them suited to several applications, including battery-
powered applications.
As a result of manufacture on a CMOS submicron process,
these DACs offer excellent 4-quadrant multiplication
characteristics of up to 12 MHz.
These DACs use a double-buffered, 3-wire serial interface that
is compatible with SPI®, QSPI™, MICROWIRE™, and most DSP
interface standards. Upon power-up, the internal shift register
and latches are filled with 0s, and the DAC output is at zero scale.
1 U.S. Patent Number 5,689,257.
FUNCTIONAL BLOCK DIAGRAM
VDD
VREF
AD5450/
AD5451/
AD5452/
AD5453
R
8-/10-/12-/14-BIT REF
R-2R DAC
RFB
IOUT1
POWER-ON
RESET
DAC REGISTER
INPUT LATCH
SYNC
SCLK
SDIN
CONTROL LOGIC
AND INPUT SHIFT
REGISTER
GND
Figure 1.
The applied external reference input voltage (VREF) determines
the full-scale output current. These parts can handle ±10 V
inputs on the reference, despite operating from a single-supply
power supply of 2.5 V to 5.5 V. An integrated feedback resistor
(RFB) provides temperature tracking and full-scale voltage
output when combined with an external current-to-voltage
precision amplifier.
The AD5450/AD5451/AD5452/AD5453 DACs are available in
small 8-lead TSOT, and the AD5452/AD5453 are also available
in MSOP packages. The AD5453 also comes in 8-lead LFCSP.
The EV-AD5443/46/53SDZ evaluation board is available for
evaluating DAC performance. For more information, see the UG-
327 evaluation board user guide.
Rev. G
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2005–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD5450/AD5451/AD5452/AD5453
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
VREF = 10 V, temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
Update Rate
VDD = 2.5 V to 5.5 V
50
20
8
8
8
5
4.5
5
30
2.7
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
MSPS
1 Guaranteed by design and characterization, not subject to production test.
Description
Maximum clock frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK active edge setup time
Data setup time
Data hold time
SYNC rising edge to SCLK active edge
Minimum SYNC high time
Consists of cycle time, SYNC high time, data setup, and
output voltage settling time
SCLK
SYNC
DIN
t8
t4
DB15
t6
t5
t1
t2 t3
t7
DB0
Figure 2. Timing Diagram
Rev. G | Page 5 of 28
5 Page 
Data Sheet
2.5
TA = 25°C
2.0
1.5
1.0
0.5
0
0
VDD = 5V
VDD = 3V
123
INPUT VOLTAGE (V)
4
Figure 24. Supply Current vs. Logic Input Voltage
5
0.7
ALL 1s
ALL 0s
0.6
0.5
VDD = 5V
0.4
0.3
0.2
VDD = 3V
0.1
0
–40 –20
0
20 40 60 80 100 120
TEMPERATURE (°C)
Figure 25. Supply Current vs. Temperature
6
TA = 25°C
AD5452
LOADING 010101010101
5
4
3
VDD = 5V
2
1
VDD = 3V
0
1 10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
Figure 26. Supply Current vs. Update Rate
AD5450/AD5451/AD5452/AD5453
1.8
TA = 25°C
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.5 3.0
VIH VIL
3.5 4.0 4.5
VOLTAGE (V)
5.0
5.5
Figure 27. Threshold Voltage vs. Supply Voltage
10
0 ALL ON
DB13
–10 DB12
–20 DB11
DB10
–30 DB9
DB8
–40 DB7
–50 DB6
DB5
–60 DB4
DB3
–70 DB2
–80
10k
100k
TA = 25°C
LOADING
ZS TO FS
VDD = 5V
VREF = ±3.5V
CCOMP = 1.8pF
AD8038 AMPLIFIER
1M
FREQUENCY (Hz)
10M
100M
Figure 28. Reference Multiplying Bandwidth vs. Frequency and Code
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8 TA = 25°C
VDD = 5V
–1.0 VREF = ±3.5V
CCOMP = 1.8pF
AD8038 AMPLIFIER
–1.2
10k 100k
1M
FREQUENCY (Hz)
10M
100M
Figure 29. Reference Multiplying Bandwidth—All 1s Loaded
Rev. G | Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD5451.PDF ] | |
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